Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 24. Asynchronous multiplexed SRAM/NOR write timings
t
wNE
FSMC_NEx
FSMC_NOE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(WENL)
FSMC_NWE
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:16]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[3:0]
FSMC_AD[15:0]
NBL
t
t
h(Data_NW)
t
v(A_NE)
v(Data_NL)
Address
Data
t
th(AD_NADV)
v(NADV_NE)
t
w(NADV)
FSMC_NADV
tdis(AD_NADV)
ai14891
(1)
Table 32. Asynchronous multiplexed SRAM/NOR write timings
FSMC - Asynchronous multiplexed SRAM/NOR write timings
VDD_IO = V and CL = 15 pF
Symbol
tw(
Parameter
Min
Max
Unit
FSMC_NE low time
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
tCK/ns
ns
NE
)
tv(
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
NWE_NE
)
tw(
NWE
)
th(
NE_NWE
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
)
tv(
tv(
TBD
TBD
TBD
A_NE
)
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
tCK/ns
tCK/ns
ns
NADV_NE
)
tw(
NADV
)
th(
AD_NADV
FSMC_AD (address) valid hold time after FSMC_NADV high TBD
FSMC_AD (address) disable time after FSMC_NADV high
)
tdis(
TBD
TBD
AD_NADV
)
th(
tv(
th(
tv(
th(
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NADV high to Data valid
TBD
A_NWE
)
BL_NE
)
TBD
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
BL_NWE
)
Data_NADV
Data_NWE
)
Data hold time after FSMC_NWE high
)
1. TBD = to be determined.
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