STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Figure 23. Asynchronous non-multiplexed SRAM/NOR read timings
t
w(NE)
FSMC_NE
t
t
t
h(NE_NOE)
w(NOE)
v(NOE_NE)
FSMC_NOE
FSMC_NWE
tv(A_NE)
t
h(A_NOE)
FSMC_A[25:0]
Address
NBL
tv(BL_NE)
t
h(BL_NOE)
FSMC_NBL[3:0]
t
h(Data_NE)
t
t
su(Data_NOE)
h(Data_NOE)
t
su(Data_NE)
Data
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
FSMC_NADV(1)
ai14991
1. Mode 2/B, C and D only.
(1)
Table 31. Asynchronous non-multiplexed SRAM/NOR read timings
VDD_IO = V and CL = 15 pF
Symbol
Parameter
FSMC_NE low time
Min
Max
Unit
tw(
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
tCK/ns
ns
NE
)
tv(
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
NOE_NE
)
tw(
NOE
)
th(
tv(
th(
tv(
th(
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NOE high
Data to FSMC_NEx high setup time
Data to FSMC_NOEx high setup time
Data hold time after FSMC_NOE high
Data hold time after FSMC_NEx high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
NE_NOE
)
TBD
TBD
A_NE
)
TBD
tCK/ns
ns
A_NOE
)
BL_NE
)
TBD
TBD
TBD
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
tCK/ns
ns
BL_NOE
)
tsu(
tsu(
th(
Data_NE
)
Data_NOE
)
Data_NOE
)
th(
Data_NE
)
tv(
TBD
TBD
tCK/ns
tCK/ns
NADV_NE
)
tw(
NADV
)
1. TBD = to be determined.
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