Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Table 33. Asynchronous multiplexed SRAM/NOR read timings
VDD_IO = V and CL = 15 pF
Symbol
tw(
Parameter
Min
Max
Unit
FSMC_NE low time
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
tCK/ns
tCK/ns
ns
NE
)
tv(
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
NOE_NE
)
tw(
NOE
)
th(
FSMC_WEN high to FSMC_NE high hold time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
NE_WEN
NE_NOE
)
th(
tv(
tv(
)
TBD
TBD
TBD
A_NE
)
TBD
TBD
tCK/ns
tCK/ns
NADV_NE
)
tw(
NADV
)
FSMC_AD (address) valid hold time after FSMC_NADV
high
th(
AD_NADV
TBD
tCK/ns
)
tdis(
FSMC_AD (address) disable time after FSMC_NADV high
Address hold time after FSMC_NOE high
FSMC_BL hold time after FSMC_NOE high
FSMC_NEx low to FSMC_BL valid
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
ns
AD_NADV
)
th(
th(
tv(
TBD
TBD
A_NOE
)
BL_NOE
)
BL_NE
)
tsu(
tsu(
th(
Data to FSMC_NEx high setup time
TBD
TBD
TBD
TBD
tCK/ns
tCK/ns
ns
Data_NE
)
Data to FSMC_NOE high setup time
Data_NOE
)
Data hold time after FSMC_NEx high
Data hold time after FSMC_NOE high
Data_NE
)
th(
Data_NOE
ns
)
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STMICROELECTRONICS [ ST ]
