Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
(1)
Table 34. Synchronous multiplexed NOR/PSRAM read timings
VDD_IO = V and CL = 15 pF
Symbol
tw(CLK)
Parameter
Min
Max
Unit
FSMC_CLK period
TBD
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(CLKH-NExL)
td(CLKH-NExH)
td(
FSMC_CLK high to FSMC_NEx low (x = 0...2)
FSMC_CLK high to FSMC_NEx high (x = 0...2)
FSMC_CLK high to FSMC_NADV low
TBD
TBD
-
-
TBD
CLK NADVL
H-
)
td(CLKH-NADVH) FSMC_CLK high to FSMC_NADV high
TBD
-
-
td(CLKH-AV)
td(CLKH-AIV)
FSMC_CLK high to FSMC_Ax valid (x = 16...25)
FSMC_CLK high to FSMC_Ax invalid (x = 16...25)
TBD
TBD
-
-
td(CLKH-NWEL) FSMC_CLK high to FSMC_NWE low
td(CLKH-NWEH) FSMC_CLK high to FSMC_NWE high
TBD
TBD
-
-
td(CLKH-NOEL)
FSMC_CLK high to FSMC_NOE low
TBD
td(CLKH-NOEH) FSMC_CLK high to FSMC_NOE high
TBD
-
-
td(CLKH-ADV)
td(CLKH-ADIV)
tsu(ADV-CLKH)
th(CLKH-ADV)
FSMC_CLK high to FSMC_AD[15:0] valid
TBD
FSMC_CLK high to FSMC_AD[15:0] invalid
FSMC_A/D[15:0] valid data before FSMC_CLK high
FSMC_A/D[15:0] valid data after FSMC_CLK high
TBD
TBD
TBD
-
-
-
tsu(NWAITV-
FSMC_NWAIT valid before FSMC_CLK high
TBD
TBD
-
-
ns
ns
CLKH)
th(CLKH-NWAITV) FSMC_NWAIT valid after FSMC_CLK high
1. TBD = to be determined.
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STMICROELECTRONICS [ ST ]
