Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.10
FSMC characteristics
All the timing characteristics are relative to the FSMC_CLK signal for synchronous
SRAM/NOR Flash memory accesses.
Figure 22. Asynchronous non-multiplexed SRAM/NOR write timings
t
w(NE)
FSMC_NEx
FSMC_NOE
FSMC_NWE
t
t
t
h(NE_NWE)
v(NWE_NE)
w(NWE)
t
tv(A_NE)
h(A_NWE)
FSMC_A[25:0]
Address
tv(BL_NE)
t
h(BL_NWE)
FSMC_NBL[3:0]
NBL
t
t
v(Data_NE)
h(Data_NWE)
Data
FSMC_D[15:0]
t
v(NADV_NE)
t
w(NADV)
(1)
FSMC_NADV
ai14990
1. Mode 2/B, C and D only.
(1)
Table 30. Asynchronous non-multiplexed SRAM/NOR write timings
VDD_IO = V and CL = 15 pF
Symbol
Parameter
FSMC_NE low time
Min
Max
Unit
tw(
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tCK/ns
tCK/ns
tCK/ns
tCK/ns
ns
NE
)
tv(
FSMC_NEx low to FSMC_NWE low
FSMC_NWE low time
WEN_NE
)
tw(
NWE
)
th(
tv(
th(
tv(
th(
tv(
th(
tv(
FSMC_NWE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
Address hold time after FSMC_NWE high
FSMC_NEx low to FSMC_BL valid
FSMC_BL hold time after FSMC_NWE high
FSMC_NEx low to Data valid
NE_NWE
)
TBD
TBD
TBD
A_NE
)
TBD
TBD
TBD
tCK/ns
ns
A_NWE
)
BL_NE
)
tCK/ns
tCK/ns
tCK/ns
tCK/ns
tCK/ns
BL_NWE
)
Data_NE
)
Data hold time after FSMC_NWE high
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
Data_NWE
)
TBD
TBD
NADV_NE
)
tw(
NADV
)
1. TBD = to be determined.
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