STLC60135
Utopia Level 2 Signals
The physical chip sends cell data towards the
ATM layer chip.
The ATM layer chip polls the status of the fifo of
the physical layer chip.
STLC60135 Utopia Level 2 MPHY Operation
Utopia level 2 MPHY operation can be done by
various interface schemes. The STLC60135 sup-
ports only the required mode, this mode is re-
ferred to as ”Operation with 1 TxClav and 1
RxClav”.
The cell exchange proceeds like:
a) The physical layer chip signals the availability
of a cell by asserting RxClav when polled by the
ATM chip.
PHY Device Identification
b) The ATM chips selects a physical layer chip,
The STLC60135 holds 2 PHY layer Utopia ports,
one is dedicated to the fast data channel, the
other one to the interleaved data channel. The
associated PHY address is specified by the
PHY_ADDR_x fields in the Utopia PHY address
register. Beware that an incorrect address con-
figuration may lead to bus conflicts. A feature is
defined to disable (tri-state) all outputsof the Uto-
pia interface. It is enabled by the TRI_STATE_EN
bit in the Rx_interface control register.
then starts the transfer by asserting RxEnb*.
c) If the physical layer chip has data to send, it
puts them on the RxData line the cycle after it
sampled RxEnb* active. It also advances the off-
set in the cell. If the data transferred is the first
byte of a cell, RxSOC is 1b at the time of the data
transfer, 0b otherwise.
d) The ATM chip accepts the data when they are
available. If RxSOC was 1b during the transfer, it
resets its internal offset pointer to the value 1,
otherwise it advances the offset in the cell.
Pin Description Utopia 2 (Receive Interface)
Name Type
Meaning
Usage
Remark
RxClav
RxEnb*
RxClk
O
Receive Cell available
Signals to the ATM chip that the
STLC60135 has a cell ready for
transfer
Remains active for the entire cell
transfer
I
Receive Enable
Signals to the physical layer that
the ATM chip will sample and
accept data during next clock cycle (high)
Gives the timing signal for the
transfer, generated by ATM layer
chip.
RxData and RxSOC could be tri-
state when RxEnb* is inactive
I
Receive Byte Clock
RxData
RxSOC
O
O
Receive Data (8 bits)
Receive Start Cell
ATM cell data, from physical layer
chip to ATM chip, byte wide.
Identifies the cell boundary on
RxData
Indicate to the ATMlayer chip that
RxData contains the first valid byte
of a cell.
RxAddr
RxRef *
I
Receive Address (5 bits) Use to select the port that will be
active or polled
O
Reference Clock
8kHz clocktransported over the
network
*Active low signal
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STMICROELECTRONICS [ ST ]
