STLC60135
Figure 19. TimingSpecification(Utopia 1)
CLOCK
T6,T8
T5,T7
SIGNAL
(at input)
SIGNAL
(highz)
T11
T9
T12
T10
D98TL331
control signals are available to match the band-
width constraints of the physical layer and the
ATM layer. The UTOPIA level 2 supports point to
multipoint configurations by introducing on ad-
dressing capability and by making a distinction
between polling and selecting a device:
- the ATM chip polls a specific physical layer chip
by putting its address on the address bus when
the Enb* line is asserted. The addressed physical
layer answers the next cycle via the Clav line re-
flecting its status at that time.
- the ATM chip selects a specific physical layer by
putting its address on the address bus when the
Enb* line is deasserted and asserting the Enb*
line on the next cycle. The addressed physical
layer chip will be the target or source of the next
cell transfer.
DIGITAL INTERFACE
Utopia Level 2 Interface
The ATM forum takes the ATM layer chip as a
reference. It defines the direction from ATM to
physical layer as the Transmit direction. The di-
rection from physical layer to ATM is the Receive
direction. Figure 20 shows the interconnection
between ATM and PHY layer devices, the op-
tional signals are not supportedand not shown.
The UTOPIA interface transfers one byte in a sin-
gle clock cycle, as a result cells are transferred in
53 clockcycles.
Both transmit and receive interfaces are synchro-
nized on clocks generated by the ATM layer chip,
and no specific relationshipbetween Receive and
Transmit clock is assumed, they must be re-
garded as mutually asynchronous clocks. Flow
Figure 20. Signal at Utopia Level 2 Interface
PHY
ATM
RxADDR
RxCLAV
RxENB*
RxCLK
5
1
PHY
RECEIVE
ATM
RECEIVE
RxDATA
RxSOC
RxREF*
8
TxADDR
TxCLAV
TxENB*
TxCLK
5
1
PHY
TRANSMIT
ATM
TRANSMIT
TxDATA
TxSOC
TxREF*
8
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STMICROELECTRONICS [ ST ]
