欢迎访问ic37.com |
会员登录 免费注册
发布采购

STLC60135 参数 Datasheet PDF下载

STLC60135图片预览
型号: STLC60135
PDF下载: 下载PDF文件 查看货源
内容描述: TOSCA ADSL DMT收发器 [TOSCA ADSL DMT TRANSCEIVER]
分类和应用:
文件页数/大小: 25 页 / 191 K
品牌: STMICROELECTRONICS [ ST ]
 浏览型号STLC60135的Datasheet PDF文件第11页浏览型号STLC60135的Datasheet PDF文件第12页浏览型号STLC60135的Datasheet PDF文件第13页浏览型号STLC60135的Datasheet PDF文件第14页浏览型号STLC60135的Datasheet PDF文件第16页浏览型号STLC60135的Datasheet PDF文件第17页浏览型号STLC60135的Datasheet PDF文件第18页浏览型号STLC60135的Datasheet PDF文件第19页  
STLC60135  
tion of RxClk, ie the ATM layer chip samples all  
RxData and RxSOC on the rising edge of RxSOC  
on the rising edge of RxClk.  
When RxEnb is asserted, the STLC60135 reads  
data from its internal fifo and presents it on  
RxData and RxSOC on each low-to-high transi-  
Pin Description  
Name  
Type  
Meaning  
Usage  
Remark  
TxClav  
O
Transmit Cell available Signals to the ATM chip that the  
physical layer chip is ready to  
Remains active for the entire cell  
transfer  
accept a complete cell  
TxEnb*  
TxClk  
I
I
Transmit Enable  
Signals to the STLC60135 that  
TxData and TxSOC are valid  
Transmit Byte Clock  
Gives the timing signal for the  
transfer, generated by ATM layer  
chip.  
TxData  
I
Transmit Data (8bits)  
ATM cell data, from ATM layer chip  
to STLC60135, byte wide. TxData  
[7] is the MSB.  
TxSOC  
TxRef *  
I
I
Transmit Start of Cell  
Reference Clock  
Identifies the cell boundary on  
TxData  
TxData contains the first validbyte  
of the cell.  
8kHz clock from the ATM layer chip  
*Active low signal  
The STLC60135 samples TxData and TxSOC  
signals on the rising edge of TxClk, if TxEnb is  
asserted.  
RxData, RxSOC, RxClav AC electrical charac-  
teristics  
TxClk, RxClk, AC electricalcharacteristics  
Symbol  
Parameters  
Min Max Unit  
Symbol  
Parameters  
Clock frequency  
Clock duty cycle  
Clock peak to peak jitter  
Clock rise fall time  
Load  
Min Max Unit  
T7  
Input set-up time to  
TxClk  
10  
ns  
F
1.5  
40  
25 MHz  
T8  
T9  
Hold time to Tx Clk  
1
ns  
ns  
Tc  
Tj  
Trf  
L
60  
5
%
%
Signal going low  
impedance to RxClk  
10  
4
ns  
pF  
T10  
T11  
T12  
L
Signal going High  
impedance to RxClk  
0
1
1
ns  
ns  
ns  
pF  
100  
Signal going low  
impedance to RxClk  
TxData, TxSOC, AC electrical characteristics  
Signal going High  
impedance to RxClk  
Symbol  
Parameters  
Min Max Unit  
T5  
T6  
L
Input set-up time to TxClk 10  
ns  
ns  
pF  
Load  
100  
Hold time to TxClk  
Load  
1
100  
Figure 18. Timing (Utopia 1 Transmit Interface)  
TxCLK  
TxSOC  
TxENB  
X
H1  
H2  
P44  
P45  
P46  
P47  
P48  
X
TxDATA  
TxCLAV  
D98TL371  
15/25