STLC60135
Table 3: Master Clock (MCLK) AC ElectricalCharacteristics
Symbol
F
Parameter
Clock Frequency
Test Condition
Min.
Typ.
35.328
28.3
Max.
Unit
MHz
ns
Tper
Th
Clock Period
Clock Duty Cycle
40
60
%
Table 4: AFTXD, AFTXED, CLWD AC Electrical Characteristics
Symbol
Tv
Parameter
Data Valid Time
Data Valid Time
Test Condition
Min.
Typ.
Typ.
Max.
10
Unit
ns
0
0
Tc
10
ns
Table 5: AFRXD AC Electrical Characteristics
Symbol
Ts
Parameter
Data setup Time
Data hold Time
Test Condition
Min.
Max.
Unit
ns
5
5
Th
ns
17
19
21
23
24
25
27
28
30
31
32
33
34
35
38
39
41
42
44
45
46
47
48
50
51
52
53
55
56
58
60
AD_11
AD_12
PCLK
AD_13
AD_14
AD_15
BE1
B
B
I
Tests, Clock, JTAG Interface
- Mclk: Master Clock (35.328MHz) generated by
VCXO
B
B
B
I
- ATM receive interface, asynchronous clock gen-
erated by Utopia Master
- ATM transmit interface, asynchronous clock
generated by Utopia Master
- ATC clock (Pclk): external asynchronous clock
(synchronous with ATC in case of i960 specific in-
terface)
JTAG TP interface: Standard Test Access Port,
Used with the boundary scan for chip and board
testing.
This JTAG TAP interface consists in 5 signals:
TDI, TDO, TCK & TMS.
ALE
C
I
CSB
WR_RDB
RDYB
I
O
I
OBC_TYPE
INTB
O
I
RESETB
TSRTB: Test Reset, reset the TAP controller.
TRSTB is an active low signal.
U_RxData_0
U_RxData_1
U_RxData_2
U_RxData_3
U_RxData_4
U_RxData_5
VSS
B
B
B
B
B
B
Table 6: Boundary Scan Chain Sequence
Sequence
Number
Mnemonic
Pin BS Type
2
3
AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8
AD_9
AD_10
B
B
B
B
B
B
B
B
B
B
B
U_RxData_6
U_RxData_7
U_RxADDR_0
U_RxADDR_1
U_RxADDR_2
U_RxADDR_3
U_RxADDR_4
GP_IN_0
B
B
I
4
6
I
7
I
9
I
10
12
13
14
16
I
i
GP_IN_1
I
U_RxRefB
O
21/25
STMICROELECTRONICS [ ST ]
