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STLC60135 参数 Datasheet PDF下载

STLC60135图片预览
型号: STLC60135
PDF下载: 下载PDF文件 查看货源
内容描述: TOSCA ADSL DMT收发器 [TOSCA ADSL DMT TRANSCEIVER]
分类和应用:
文件页数/大小: 25 页 / 191 K
品牌: STMICROELECTRONICS [ ST ]
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STLC60135  
Utopia Level 1 Interface  
The Utopia Level 2 supports point to multipoint  
configurationsby introducing an addressingcapa-  
bility and by making distinction between polling  
and selecting a device.  
The ATM forum takes the ATM layer chip as a  
reference. It defines the direction from ATM to  
physical layer as the Transmit direction. The di-  
rection from physical layer to ATM is the Receive  
direction. Figures 15 & 16 show the interconnec-  
tion between ATM and PHY layer devices, the  
optional signals are not supported and not  
shown.  
Figure 15. ReceiveInterface  
PHY  
ATM  
RxREF*  
RxCLAV  
RxENB*  
RxCLK  
The Utopia interface transfers one byte in a sin-  
gle clock cycle, as a result cells are transformed  
in 53 clock cycles.  
Both transmit and receive are synchronized on  
clocks generated by the ATM layer chip, and no  
specific relationship between receive and transmit  
clocks is required.  
PHY  
RECEIVE  
CELL  
RECEIVE  
RxDATA  
RxSOC  
8
In this mode, the STLC60135 can only support  
one data flow : either interleaved or fast .  
Figure 17. Timing (Utopia 1 Receive Interface)  
D98TL330  
Figure 16. TransmitInterface  
PHY  
ATM LAYER  
RxCLK  
RxSOC  
RxENB  
TxREF*  
TxCLAV  
TxENB*  
PHY  
TRANSMIT  
CELL  
TRANSMIT  
X
H1  
H2  
P44  
P45  
P46  
P47  
P48  
X
TxCLK  
TxDATA  
TxSOC  
RxDATA  
RxCLAV  
8
D98TL369  
D98TL370  
Pin Description  
Name  
Type  
Meaning  
Usage  
Remark  
RxClav  
O
Receive Cell available Signals to the ATM chip that the  
STLC60135 has a cell ready for  
transfer  
Remains active for the entire cell  
transfer  
RxEnb*  
RxClk  
I
Receive Enable  
Signals to the STLC60135 that the  
ATM chip will sample and accept  
data during next clock cycle  
RxData and RxSOC could be tri-  
state when RxEnb* is inactive  
(high). Active low signal  
I
Receive Byte Clock  
Receive Data (8bits)  
Receive Start Cell  
Reference Clock  
Gives the timing signal for the  
transfer, generated by ATM layer  
chip.  
ATM cell data, from STLC60135  
chip to ATM chip, byte wide. Rx  
Data [7] is the MSB.  
RxData  
RxSOC  
RxRef *  
O
O
O
Identifies the cell boundary on  
RxData  
Indicate to the ATM layer chip that  
RxData contains the first valid byte  
of a cell.  
8 kHz clock transported over the  
network  
Active low signal  
*Active low signal  
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