STLC60135
Generic processor interface Cycle Timing
All AC characteristicsare indicated for a 100pF capacitive load.
Symbol
Parameters
Rise & Fall time (10% to 90%)
ALE pulse width
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
tr & tf
3
Talew
Tavs
12
10
10
0
Address Valid setup time
Address Valid Hold time
ALE to CSB
Tavh
Tale2cs
Tale2Z
Tcs2rdy
Tcsre
ALE to high Z state of address bus
CSB to RDYB asserted
Access Time
50
60
900
Tcs2wr
Twr2d
Trdy2wr
Tdvs
CSB to WRB
0
WRB to data
15
RDYB to WRB
0
data setup time
10
Tdvh
data hold time
1/2Tmclk
Tmclk
Twr2cs
Tcs2rd
Trdy2rd
Trd2cs
Tmclk
WRB to CSB
-10
0
CSB to RDB
RDY to RDB
0
RDB to CSB
-10
Master clock Timing
Figure 14. Waveforms
T
alew
ALE
T
avs
T
avh
AD(15:0)
D98TL326
Cells are stored in a fifo, 2 interfaces submodules
can extract data from the fifo. Byte streams are
dumped on the bitstream interface (with no fifo).
Generic Processor Interface Pins and Func-
tional Description
Name
Type
Function
3 kinds of interface are allowed
Utopia Level 1
AD[0..15] I/O Multiplexed address / data bus
ALE
I
I
I
I
Address Latch Enable
Read cycle indication
Write cycle indication
Chip Select
Utopia Level 2
Bitstreambased on a proprietaryexchange
RDB
WRB
CSB
RDYB
INTB
The interface selection is programmed by writing
the Utopia PHY address register.
Only one interface can be enabled in a ST60135
configuration.
OZ Bus cycleready indication
Interrupt
O
Utopia Level 1 supports only one PHY device.
Utopia Level 2 supports multi-PHY devices (See
Utopia Level 2 specifications).
Digital interface ATM or serial
Digital Interface for data to the loop before modu-
lation and from the loop after demodulation.
This interfacecollects cells (from the cell based func-
tion module) or a byte stream (from the deframer).
Each buffer provides storage for 8 ATM cells (both
directionsfor Fast and Interleaved channel).
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STMICROELECTRONICS [ ST ]
