STLC60135
SLAP INTERFACE, AC ElectricalCharacteristics
Symbol
Tper
Th
Parameter
Clock Period
Test Condition
refer to MCLK
Min.
Typ.
Max.
Unit
ns
Clock High
Clock Low
Setup
11
11
3
ns
Tl
ns
Ts
ns
Thd
Td
Hold
2
ns
Data Delay
20pF load
3
6
ns
Analog Front End Control Interface
The STLC60135 fetches the 16 bit word to be
multiplexed on AFTXD from the Tx Digital Front-
End module.
The Analog Front End Interface is designed to be
connected to the STLC60134 Analog Front End
component.
Receive Interface
The 16 bit receive word is multiplexed on 4
AFRXD input signals. As a result 4 cycles are
needed to transfer 1 word. Refer to Table 2 for
the bit / pin allocation for the 4 cycles. The first of
4 cycles is identified by the CLWD must repeat
after 4 MCLK cycles.
Transmit Interface
The 16 bit words are multiplexed on 4 AFTXD
output signals. As a result 4 cycles are needed to
transfer 1 word. Refer to table 1 for the bit/pin al-
location for the 4 cycles. The first of 4 cycles is
identified by the CLWD signal. Refer to Figure 26.
Figure 27. TransmittWord TimingDiagram
Table 1: Transmitted Bits Assigned to Signal /
Time Slot
MCLK
CLWD
Cycle 0 Cycle 1 Cycle 2 Cycle 3
AFTXD[0]
AFTXD[1]
AFTXD[2]
AFTXD[3]
GP_OUT
b0
b1
b2
b3
t0
b4
b5
b6
b7
t1
b8
b9
b12
b13
b14
b15
t3
AFTXD
AFTXED
b10
b11
t2
Cycle0 Cycle1 Cycle2 Cycle3
GP_OUT
Test0 Test1 Test2 Test3
D98TL320
Figure 28. ReceiveWord TimingDiagram
Table 2: Transmitted Bits Assigned to Signal /
Time Slot
MCLK
CLWD
Cycle 0 Cycle 1 Cycle 2 Cycle 3
AFRXD[0]
AFRXD[1]
AFRXD[2]
AFRXD[3]
GP_IN
b0
b1
b2
b3
t0
b4
b5
b6
b7
t1
b8
b9
b12
b13
b14
b15
t3
AFRXD
b10
b11
t2
Cycle0 Cycle1 Cycle2 Cycle3
GP_IN(0)
Test0 Test1 Test2 Test3
D98TL321
Figure 29. TransmitInterface
Figure 30. ReceiveInterface
MCLK
Tv
MCLK
Ts
AFTXD
AFTXED
Tc
Th
AFRXD
D98TL323
CLWD
D98TL322
20/25
STMICROELECTRONICS [ ST ]
