STLC60135
The processorinterface in i960 mode
The i960 mode supports a synchronousbus inter-
face protocol.
Address and data are multiplexed. The processor
is bus master and the STLC60135 is bus slave.
Synchronous means that all signals are synchro-
nous with the input clock PCLK pin.
The bus cycles are directly started and driven by
the processor. Addresses (BE1, AD[2..15]) have
to be present before ATC asserts the ALE signal.
Processor Interface Pins and Functional De-
scription i960 mode
Name
Type
Function
Multiplexed Address/Data bus
Address bit 1
AD[0...15] I/O
BE1
I
ALE
I
I
Address Latch Enable
Access direction: Write (1), Read (0)
Processor Clock
WR_RDB
PCLK
CSB
I
I
Chip Select
STLC60135 latches the address on the falling
edge of ALE signal.
The RDYB output is synchronousto PCLK.
RDYB
INTB
OZ
O
Bus cycle ready indication
Interrupt
A bus cycle consists of an Access cycle (Ta),
Wait cycles (Tw), Data cycle (Td) and Recovery
cycle (Tr).
Generic Interface
This interface is suitable for a number of proces-
sors using a multiplexed Address/databus. In this
case, synchronisation of the input signals with
PCLK pin is not necessary.
Figure 12. Generic ProcessorInterface Write Timing Cycle
T
alew
ALE
CSB
T
wr2cs
T
avs
T
avh
AD(15-0)
T
wr2d
T
dvh
T
ale2cs
T
wdvd
WRB
T
cs2rdy
T
mclk
T
T
wrw
cs2wr
READY
T
csre
T
rdy2wr
RDB
D98TL327
Figure 13. Generic ProcessorInterface Read Timing Cycle
T
T
ale2Z
alew
ALE
CSB
T
rd2cs
T
avs
T
avh
AD(15-0)
T
T
dvh
T
wr2d
ale2cs
T
wdvd
RDB
T
csrd
T
mclk
T
wrw
READY
T
csrs
T
T
rdy2dr
csre
WRB
D98TL328
12/25
STMICROELECTRONICS [ ST ]
