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STLC60135 参数 Datasheet PDF下载

STLC60135图片预览
型号: STLC60135
PDF下载: 下载PDF文件 查看货源
内容描述: TOSCA ADSL DMT收发器 [TOSCA ADSL DMT TRANSCEIVER]
分类和应用:
文件页数/大小: 25 页 / 191 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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STLC60135
The DSTU schedulers execute a program, con-
trolled by program opcodes and a set of vari-
ables, the most important of which are real time
counters. The transmit and receive sequencers
are completely independent and run different pro-
grams. An independent set of variables is as-
signed to each of them. The sequencer programs
can be updated in real time.
STLC60135 interfaces
Overview
Figure 9. STLC60135 interfaces
AFE INTERFACE TO
ADSL LINE (STLC60134)
Processor Interface (ATC)
The STLC60135 is controlled and configured by
an external processor across the processor inter-
face. All programmable coefficients and parame-
ters are loaded through this path.
The ADSL initialization is also controlled by this
interface
Two interface types are supported; A generic
asynchronous interface (i.e. PowerPC or any mi-
croprocessor interface) and a specific i960 inter-
face. The choice is made by the OBC_TYPE pin.
(0 selects i960 type interface, 1 selects generic
access).
Data and addresses are multiplexed.
STLC60135 works in 16 bits data access, so ad-
dress bit 0 is not used. Address bit 1 is not multi-
plexed with data. It has its own pin : BE1
Byte acces are not supported. Access cycle read
or write are always in 16 bits data wide, ie bit ad-
dress A0 is always zero value. The interrupt re-
quest pin to the processor is INTB, and is an
Open Drain output.
Tle STLC60135 supports both little and big en-
dian. The default feature is big endian.
RESET
PROCESSOR
INTERFACE
(ATC)
JTAG
STLC60135
CLOCK
D98TL368A
DIGITAL INTERFACE
UTOPIA/BITSTREAM INTERFACE
Figure 10. Processor Interface Read cycle i960 mode
Ta
Tw
Tw
Tw
Tw
Td
Tr
Ta
PCLK
ALE
CSB
Wait
RDYB
ADDR
DATAin
AD
ATC samples data
BE1
WR_RDB
ADD(1)
D98TL324A
(1): The RDYB output is continuously
in tri-state, except for 2 cycles
Figure 11. Processor Interface Write Cycle i960 mode
Ta
Tw
Tw
Tw
Tw
Td
Tr
Ta
PCLK
ALE
CSB
Wait
RDYB
ADDR
DATA out
AD
STLC60135 samples data
BE1
WR_RDB
ADD(1)
D98TL325A
(1): The RDYB output is continuously
in tri-state, except for 2 cycles
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