STLC60135
Main Block Description
The following drawings describe the sequence of
functions performed by the chip.
DSP Front-End
The DSP Front-End contains 4 parts in the re-
ceive direction: the Input Selector, the Analog
Front-End Interface, the Decimator and the Time
Equalizer. The input selector is used internally to
enable test loopbacks inside the chip. The Analog
Front-End lnterface transfers 16-bit words, multi-
plexed on 4 input/output signals. Word transfer is
carried out in 4 clock cycles.
The Decimator receive 16-bits samples at 8.8
MHz (as sent by the Analog Front-End chip:
STLC60134) and reduces this rate to 2.2 MHz.
The Time Equalizer (TEQ) module is a FIR filter
with programmable coefficients. Its main purpose
is to reduce the effect of Inter-Symbol Interfer-
ences (ISI) by shortening the channel impulse re-
sponse.
Both the Decimator and TEQ can be bypassed.
In the transmit direction, the DSP Front-End in-
cludes: sidelobe filtering, clipping, delay equaliza-
tion and interpolation. The sidelobe filtering and
Figure 3. DSP Front-End Receive
delay equalization are implemented by IIR Filters,
reducing the effect of echo in FDM systems. Clip-
ping is a statistical process limiting the amplitude
of the output signal, optimizing the dynamic range
of the AFE. The interpolator receives data at 2.2
MHz and generates samples at a rate of 8.8
MHz.
DMT Modem
This module is a programmable DSP unit. Its in-
struction set enables the basic functions of the
DMT algorithm like FFT, IFFT, Scaling, Rotor and
Frequency Equalization (FEQ) in compliance with
ANSI T1.413 specifications.
In the RX path, the 512-point FFT transforms the
time-domain DMT symbol into a frequency do-
main representation which can be further de-
coded by the subsequent demapping stages.
In other words, the Fast Fourier Transform proc-
ess is used to transform from time domain to fre-
quency domain (receive path). On ATU-C side,
128 time samples are processed. On ATU-R side,
1024 time samples are processed.
After the first stage time domain equalization and
FFT block an ICI (InterCarrier Interference) free
information stream turns out.
Figure 4. DSP Front-End Transmit
BYPASS
FROM
ANALOG
FRONT-END
IN
SELECT
AFE
I/F
DEC
TEQ
TO DMT
MODEM
FROM
DMT
MODEM
Filtering
Clipping
Delay
Equalizer
Interpolator
AFE
I/F
OUT
SELECT
TO ANALOG
FRONT END
D98TL382
D98TL372A
Figure 5. DMT Modem (Rx & Tx)
TRELLIS
CODING
DECODING
TO/FROM
DSP FE
FFT
IFFT
FEQ
FTG
ROTOR
MAPPER
DEMAPPER
TO/FROM
TC
FEQ
COEFFICIENTS
MONITOR
FEQ
UPDATE
MONITOR
INDICATIONS
D98TL316A
8/25
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