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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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J1850 Byte Level Protocol Decoder (JBLPD)  
J1850 BYTE LEVEL PROTOCOL DECODER (Cont’d)  
IFR3+CRC, In-Frame Response Type 3 then ap-  
pend CRC opcode.  
The IFR3 byte is attempted according to the pro-  
cedure described in section “Transmitting a type 3  
IFR”. The CRC byte is transmitted out on comple-  
tion of the transmit of the IFR3 byte.  
If this opcode sets up the last byte in an IFR3 data  
string, then the TXDATA register contents shall be  
transmitted out immediately upon completion of  
the previous IFR3 data byte followed by the trans-  
mit of the CRC byte. In this case the IFR3+CRC is  
enabled on conditions 4 and 5 listed above. Note  
that if an IFR3+CRC opcode is written, a queued  
MSG or MSG+CRC is overridden by the  
IFR3+CRC.  
The In-frame Response Type 3 then append CRC  
opcode (IFR3+CRC) is set if the user program  
wants to either initiate to transmit a single data  
byte IFR3 followed by a CRC, or transmit the last  
data byte of an IFR3 string followed by the CRC  
byte in response to a message that is currently be-  
ing received.  
The IFR3+CRC opcode transmits the contents of  
the TXDATA register followed by the computed  
CRC byte. The user program decides to set up an  
IFR3 upon receiving a certain portion of the data  
byte string of an incoming message. A previous  
write of the TXDATA register should have oc-  
curred.  
SBRK, Send Break Symbol.  
The SBRK opcode is written to transmit a nominal  
break (BRK) symbol out the VPWO pin. A Break  
symbol can be initiated at any time. Once the  
SBRK opcode is written a BRK symbol of the nom-  
inal Tv5 duration will be transmitted out the VPWO  
pin immediately. To terminate the transmission of  
an in-progress break symbol the JE bit should be  
set to a logic zero. An SBRK command is non-  
maskable, it will override any present transmit op-  
eration, and it does not wait for the present trans-  
mit to complete. Note that in the 4X mode a SBRK  
will send a break character for the nominal Tv5  
time times four (4 x Tv5) so that all nodes on the  
bus will recognize the break. A CANCEL opcode  
does not override a SBRK command.  
The J1850 block will enable the transmission of  
the first byte of an IFR3 string on these conditions:  
– 1) The CRC check is valid (otherwise the CRCE  
is set)  
– 2) The received message length is valid if ena-  
bled (otherwise the TRA is set)  
– 3) A valid EOD minimum symbol is received (oth-  
erwise the IFD may eventually get set due to  
byte synchronization errors)  
– 4) If NFL = 0 & Received Byte Count for this  
frame <=10 (otherwise TRA is set and inverted  
CRC is transmitted)  
CANCEL, No Operation or Cancel Pending Trans-  
mit.  
– 5) If not presently executing an MSG opcode  
(otherwise TRA is set, and TDUF will get set be-  
cause the transmit state machine will be expect-  
ing more data and the inverted CRC will be  
appended to this frame)  
The Cancel opcode is used by the user program to  
tell the J1850 transmitter that a previously queued  
opcode should not be transmitted. The Cancel op-  
code will set the TRDY bit. If the JBLPD peripheral  
is presently not transmitting, the Cancel command  
effectively cancels a pending MSGx or IFRx op-  
code if one was queued, or it does nothing if no  
opcode was queued. If the JBLPD peripheral is  
presently transmitting, then a queued MSGx or  
IFRx opcode is aborted and the TDUF circuit may  
take affect.  
– 6) If not presently executing an IFR1, IFR2 or  
IFR3+CRC opcodes, otherwise TRA is set (but  
no TDUF)  
– 7) If not presently receiving an IFR portion of a  
frame, otherwise TRA is set.  
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