SERIAL PERIPHERAL INTERFACE (SPI)
10.7 SERIAL PERIPHERAL INTERFACE (SPI)
10.7.1 Introduction
– MOSI: Master Out Slave In pin
– SCK: Serial Clock pin
The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
– SS: Slave select pin
To use any of these alternate functions (input or
output), the corresponding I/O port must be pro-
grammed as alternate function output.
The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another Microcontroller.
A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 120.
Refer to the Pin Description chapter for the device-
specific pin-out.
The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave.
10.7.2 Main Features
■ Full duplex, three-wire synchronous transfers
■ Master or slave operation
When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).
■ Maximum slave mode frequency = INTCLK/2.
■ Programmable prescalers for a wide range of
baud rates
■ Programmable clock polarity and phase
■ End of transfer interrupt flag
■ Write collision flag protection
■ Master mode fault protection capability.
10.7.3 General Description
Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.
Various data/clock timing relationships may be
chosen (see Figure 123) but master and slave
must be programmed with the same timing mode.
The SPI is connected to external devices through
4 alternate function pins:
– MISO: Master In Slave Out pin
Figure 120. Serial Peripheral Interface Master/Slave
SLAVE
MASTER
MSBit
LSBit
MSBit
LSBit
MISO
MOSI
MISO
MOSI
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
SPI
CLOCK
GENERATOR
SCK
SS
SCK
SS
+5V
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