SERIAL PERIPHERAL INTERFACE (SPI)
SERIAL PERIPHERAL INTERFACE (Cont’d)
10.7.4.2 Slave Configuration
When data transfer is complete:
– The SPIF bit is set by hardware
In slave configuration, the serial clock is received
on the SCK pin from the master device.
– An interrupt is generated if the SPIS and SPIE
bits are set.
The value of the SPPR register and SPR0 & SPR1
bits in the SPCR is not used for the data transfer.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPDR register is
read, the SPI peripheral returns this buffered val-
ue.
Procedure
– For correct data transfer, the slave device
must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
123.
Clearing the SPIF bit is performed by the following
software sequence:
1. An access to the SPSR register while the SPIF
bit is set.
– The SS pin must be connected to a low level
signal during the complete byte transmit se-
quence.
2. A read of the SPDR register.
– Clear the MSTR bit and set the SPOE bit to
assign the pins to alternate function.
Notes: While the SPIF bit is set, all writes to the
SPDR register are inhibited until the SPSR regis-
ter is read.
In this configuration the MOSI pin is a data input
and the MISO pin is a data output.
The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 10.7.4.6).
Transmit Sequence
The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.
Depending on the CPHA bit, the SS pin has to be
set to write to the SPDR register between each
data byte transfer to avoid a write collision (see
Section 10.7.4.4).
The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.
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