ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (SCI-A)
ASYNCHRONOUS SERIAL COMMUNICATIONS INTERFACE (Cont’d)
EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (SCIERPR)
EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (SCIETPR)
R245 - Read/Write
R246 - Read/Write
Register Page: 26
Register Page: 26
Reset Value: 0000 0000 (00h)
Reset Value:0000 0000 (00h)
Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.
Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.
7
0
7
0
ERPR7 ERPR6 ERPR5 ERPR4 ERPR3 ERPR2 ERPR1 ERPR0
ETPR7 ETPR6 ETPR5 ETPR4 ETPR3 ETPR2 ETPR1 ETPR0
Bits 7:1 = ERPR[7:0] 8-bit Extended Receive
Prescaler Register.
Bits 7:1 = ETPR[7:0] 8-bit Extended Transmit
Prescaler Register.
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 119) is divided by
the binary factor set in the SCIERPR register (in
the range 1 to 255).
The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 119) is divided by
the binary factor set in the SCIETPR register (in
the range 1 to 255).
The extended Baud Rate Generator is not used af-
ter a reset.
The extended Baud Rate Generator is not used af-
ter a reset.
10.6.6 Important Notes on SCI-A
Refer to Section 13.1.4 on page 412 and Section
13.1.5 on page 412.
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STMICROELECTRONICS [ ST ]
