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ST92F150JDV1Q6 参数 Datasheet PDF下载

ST92F150JDV1Q6图片预览
型号: ST92F150JDV1Q6
PDF下载: 下载PDF文件 查看货源
内容描述: 8月16日- BIT单电压闪存单片机系列内存, E3 TMEMULATED EEPROM , CAN 2.0B和J1850 BLPD [8/16-BIT SINGLE VOLTAGE FLASH MCU FAMILY WITH RAM, E3 TMEMULATED EEPROM, CAN 2.0B AND J1850 BLPD]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 426 页 / 3830 K
品牌: STMICROELECTRONICS [ ST ]
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ST92F124/F150/F250 - INTERRUPTS  
INTERRUPT REGISTERS (Cont’d)  
EXTERNAL INTERRUPT VECTOR REGISTER  
(EIVR)  
0: WAITN pin disabled  
1: WAITN pin enabled (to stretch the external  
memory access cycle).  
R246 - Read/Write  
Register Page: 0  
Reset value: xxxx 0110 (x6h)  
Note: For more details on Wait mode refer to the  
section describing the WAITN pin in the External  
Memory Chapter.  
7
0
V7  
V6  
V5  
V4 TLTEV TLIS IAOS EWEN  
NESTED INTERRUPT CONTROL (NICR)  
R247 - Read/Write  
Register Page: 0  
Bits 7:4 = V[7:4]: Most significant nibble of Exter-  
nal Interrupt Vector.  
These bits are not initialized by reset. For a repre-  
sentation of how the full vector is generated from  
V[7:4] and the selected external interrupt channel,  
refer to Figure 51.  
Reset value: 0000 0000 (00h)  
7
0
TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0  
Bit 7 = TLNM: Top Level Not Maskable.  
This bit is set by software and cleared only by a  
hardware reset.  
0: Top Level Interrupt Maskable. A top level re-  
quest is generated if the IEN, TLI and TLIP bits  
=1  
Bit 3 = TLTEV: Top Level Trigger Event bit.  
This bit is set and cleared by software.  
0: Select falling edge as NMI trigger event  
1: Select rising edge as NMI trigger event  
1: Top Level Interrupt Not Maskable. A top level  
request is generated if the TLIP bit =1  
Bit 2 = TLIS: Top Level Input Selection.  
This bit is set and cleared by software.  
0: Watchdog End of Count is TL interrupt source  
(the IA0S bit must be set in this case)  
1: NMI is TL interrupt source  
Bits 6:0 = HL[6:0]: Hold Level x  
These bits are set by hardware when, in Nested  
Mode, an interrupt service routine at level x is in-  
terrupted from a request with higher priority (other  
than the Top Level interrupt request). They are  
cleared by hardware at the iretexecution when  
the routine at level x is recovered.  
Bit 1 = IA0S: Interrupt Channel A0 Selection.  
This bit is set and cleared by software.  
0: Watchdog End of Count is INTA0 source (the  
TLIS bit must be set in this case)  
1: External Interrupt pin is INTA0 source  
Bit 0 = EWEN: External Wait Enable.  
This bit is set and cleared by software.  
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