ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT PRIORITY LEVEL REGISTER LOW
(SIPLRL)
Interrupt Channel
Pair
Priority Level
R253 - Read/Write
INTE0
INTE1
INTF0
INTF1
INTG0
INTG1
INTH0
INTH1
PL2E
PL2E
PL2F
PL2F
PL2G
PL2G
PL2H
PL2H
PL1E
PL1E
PL1F
PL1F
PL1G
PL1G
PL1H
PL1H
0
1
0
1
0
1
0
1
Register Page: Page 60
Reset Value : 1111 1111
7
0
PL2H PL1H PL2G PL1G PL2F PL1F PL2E PL1E
Bits 7:6 = PL2H, PL1H: INTH0,H1 Priority Level.
Bits 5:4 = PL2G, PL1G: INTG0, G1 Priority Level.
Bits 3:2 = PL2F, PL1F: INTF0, F1 Priority Level.
Bits 1:0 = PL2E, PL1E: INTE0, E1 Priority Level.
These bits are set and cleared by software.
INTERRUPT FLAG REGISTER HIGH
(SFLAGRH)
R254 - Read Only
Register Page: 60
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for even channels and at 1 for odd
channels
Reset Value : 0000 0000
7
0
Table 22. PL Bit Assignment
-
-
-
-
-
-
-
OUFI0
Interrupt Channel
3-bit Priority Level
Pair
Bit 0 = OUFI0 : Overrun flag for INTI0
INTH0
INTH1
INTG0
INTG1
INTF0
INTF1
INTE0
INTE1
PL2H
PL2H
PL2G
PL2G
PL2F
PL2F
PL2E
PL2E
PL1H
PL1H
PL1G
PL1G
PL1F
PL1F
PL1E
PL1E
0
1
0
1
0
1
0
1
This bit is set and cleared by hardware. It indicates
if more than one interrupt event occured on INTI0
before the IPI0 bit in the SIPRH register has been
cleared.
0 : No overrun
1 : Overrun has occurred on INTI0
INTERRUPT FLAG REGISTER LOW
(SFLAGRL)
R255 - Read Only
Register Page: 60
Reset Value : 0000 0000
Table 23. PL bit Meaning
PL2x
PL1x
Hardware bit
Priority
7
0
0
1
0 (Highest)
1
0
0
OUFH1 OUFH0 OUFG1 OUFG0 OUFF1 OUFF0 OUFE1 OUFE0
0
1
2
3
0
1
1
1
0
1
Bits 7:0 = OUFxx : Overrun flag for channel xx
These bits are set and cleared by hardware. They
indicate if more than one interrupt event occurs on
the associated channel before the pending bit in
the SIPRL register has been cleared.
0
1
4
5
0
1
6
7 (Lowest)
0 : No overrun
1 : Overrun has occurred on channel xx
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