ST92F124/F150/F250 - INTERRUPTS
INTERRUPT REGISTERS (Cont’d)
INTERRUPT MASK REGISTER HIGH (SIMRH)
1: The I0 pending bit will be set on the rising edge
of the interrupt line
R245 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Note: The ITEI0 bit must be set to enable the SCI-
A interrupt as the SCI-A interrupt event is a rising
edge event.
7
-
0
-
-
-
-
-
-
IMI0
INTERRUPT TRIGGER EVENT REGISTER LOW
(SITRL)
R248 - Read/Write
Bits 7:1 = Reserved.
Bit 0 = IMI0 Channel I Mask bit
Register Page: 60
Reset value: 0000 0000 (00h)
The IMI0 bit is set and cleared by software to ena-
ble or disable interrupts on channel I0 .
0: Interrupt masked
1: An interrupt is generated if the IPI0 bit is set in
the SIPRH register.
7
0
ITEH1 ITEH0 ITEG1 ITEG0 ITEF1 ITEF0 ITEE1 ITEE0
Bits 7:0 = ITExx Channel E to H Trigger Event
The ITExx bits are set and cleared by software to
define the polarity of the channel xx trigger event
0: The corresponding pending bit will be set on the
falling edge of the interrupt line
1: The corresponding pending bit will be set on the
rising edge of the interrupt line
INTERRUPT MASK REGISTER LOW (SIMRL)
R246 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
7
0
Note: The ITExx bits must be set to enable the
CAN interrupts as the CAN interrupt events are ris-
ing edge events.
IMH1 IMH0 IMG1 IMG0 IMF1
IMF0 IME1
IME0
Bits 7:0 = IMxx Channel E to H Mask bits
Note: If either a rising or a falling edge occurs on
the interrupt lines during a write access to the
ITER register, the pending bit will not be set.
The IMxx bits are set and cleared by software to
enable or disable on channel xx interrupts.
0: Interrupt masked
1: An interrupt is generated if the corresponding
IPxx bit is set in the SIPRL register.
INTERRUPT PENDING REGISTER HIGH
(SIPRH)
R249 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
INTERRUPT TRIGGER EVENT REGISTER
HIGH (SITRH)
R247 - Read/Write
7
-
0
Register Page: 60
Reset value: 0000 0000 (00h)
-
-
-
-
-
-
IPI0
7
-
0
Bits 7:1 = Reserved.
Bit 0 = IPI0 Channel I0 Pending bit
-
-
-
-
-
-
ITEI0
The IPI0 bit is set by hardware on occurrence of
the trigger event. (as specified in the ITR register)
and is cleared by hardware on interrupt acknowl-
edge.
Bits 7:1 = Reserved.
Bit 0 = ITEI0 Channel I0 Trigger Event
This bit is set and cleared by software to define the
polarity of the channel I0 trigger event
0: The I0 pending bit will be set on the falling edge
of the interrupt line
0 : No interrupt pending
1 : Interrupt pending
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