ST92F124/F150/F250 - INTERRUPTS
Figure 53. Standard Interrupt (Channels E to I) Control Bits and Vectors
ITEE0
0
X
V6
V7
V5
X
0
0
0
X
0
VECTOR
Priority level
INT E0
request
Mask bit
Pending bit IPE0
IME0
ITEE1
ITEF0
V6
V6
0
X
V7
V5
X
0
0
1
X
1
VECTOR
Priority level
INT E1
request
Mask bit
Pending bit IPE1
IME1
ITRX0
ITRX1
ITTX
0
X
V7
V5
X
0
1
0
X
0
VECTOR
Priority level
ITSCE
INT F0
request
Mask bit
Pending bit IPF0
IMF0
CAN_0 *
ITEF1
ITEG0
0
0
1
V6
V6
V7
V5
X
X
1
VECTOR
Priority level
INT F1
request
1
X
Mask bit
IMF1
Pending bit IPF1
0
1
0
V7
V5
X
X
0
VECTOR
Priority level
INT G0
request
0
X
Pending bit IPG0
Mask bit
IMG0
ITEG1
ITEH0
0
X
V6
V6
V7
V5
X
1
0
1
X
1
VECTOR
Priority level
INT G1
request
Pending bit IPG1
Mask bit
IMG1
ITRX0
ITRX1
ITTX
0
X
V7
V5
X
1
1
0
X
0
VECTOR
Priority level
ITSCE
INT H0
request
Mask bit
IMH0
Pending bit IPH0
CAN_1 *
ITEH1
ITEI0
V6
V6
0
X
V7
V5
X
1
1
1
X
1
VECTOR
Priority level
INT H1
request
Mask bit
IMH1
Pending bit IPH1
1
X
V7
V5
X
0
0
0
X
0
VECTOR
Priority level
INT I0
request
SCI-A *
Mask bit
IMI0
Pending bit IPI0
* On some devices only
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