ST92F124/F150/F250 - INTERRUPTS
EXTERNAL INTERRUPTS (Cont’d)
Figure 51. External Interrupt Control Bits and Vectors
Watchdog/Timer
End of count
IA0S
TEA0
V6
V7
V5 V4 0
0
X
0
VECTOR
Priority level
“0”
INT A0
request
0
X
X
Mask bit
Pending bit IPA0
IMA0
“1”
INT 0 pin*
INT 1 pin*
INTS
TEA1
STIM Timer
V6
V6
V7
V5 V4 0
0
X
1
VECTOR
“0”
Priority level
INT A1
request
1
X
X
Mask bit
Pending bit IPA1
IMA1
“1”
EFTIS
TEB0
TEB1
TEC0
EFT0 Timer
V7
V5 V4 0
1
X
0
VECTOR
Priority level
“1”
INT B0
request
0
X
X
INT 2 pin*
INT 3 pin*
Mask bit
Pending bit IPB0
IMB0
“0”
EFTIS
EFT1 Timer
V6
V6
V7
V5 V4 0
1
X
1
VECTOR
Priority level
“1”
INT B1
request
1
X
X
“0”
Mask bit
IMB1
Pending bit IPB1
FEIEN
3 TM
E
/Flash
“1”
“0”
V7
V5 V4 1
0
X
0
VECTOR
Priority level
INT C0
request
0
X
X
INT 4 pin*
INT 5 pin*
Pending bit IPC0
Mask bit
IMC0
SPIS
TEC1
SPI
V6
V6
V6
V7
V5 V4 1
0
X
1
VECTOR
“1”
“0”
INT C1
request
Priority level
1
X
X
Pending bit IPC1
Mask bit
IMC1
INT_SEL
RCCU
TED0
V7
V5 V4 1
1
X
0
VECTOR
Priority level
“1”
“0”
INT D0
request
0
X
X
INT 6 pin
NMI
Mask bit
IMD0
Pending bit IPD0
ID1S
V7
V5 V4 1
1
X
1
VECTOR
Priority level
“1”
“0”
INT D1
request
1
X
X
Wake-up
Controller
Mask bit
IMD1
Pending bit IPD1
WKUP
(0:15)
* Only four interrupt pins are available. Refer to Table 19 for I/O pin mapping.
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