ST92F124/F150/F250 - INTERRUPTS
ARBITRATION MODES (Cont’d)
5.5.2 Nested Mode
– All maskable interrupt requests are disabled by
clearing CICR.IEN.
The difference between Nested mode and Con-
current mode, lies in the modification of the Cur-
rent Priority Level (CPL) during interrupt process-
ing.
– CPL is saved in the special NICR stack to hold
the priority level of the suspended routine.
– Priority level of the acknowledged routine is
stored in CPL, so that the next request priority
will be compared with the one of the routine cur-
rently being serviced.
The arbitration phase is basically identical to Con-
current mode, however, once the request is ac-
knowledged, the CPL is saved in the Nested Inter-
rupt Control Register (NICR) by setting the NICR
bit corresponding to the CPL value (i.e. if the CPL
is 3, the bit 3 will be set).
– The PC low byte is pushed onto system stack.
– The PC high byte is pushed onto system stack.
– If ENCSR is set, CSR is pushed onto system
stack.
The CPL is then loaded with the priority of the re-
quest just acknowledged; the next arbitration cycle
is thus performed with reference to the priority of
the interrupt service routine currently being exe-
cuted.
– The Flag register is pushed onto system stack.
– The PC is loaded with the 16-bit vector stored in
the Vector Table, pointed to by the IVR.
Start of Interrupt Routine
– If ENCSR is set, CSR is loaded with ISR con-
tents; otherwise ISR is used in place of CSR until
iretinstruction.
The interrupt cycle performs the following steps:
Figure 48. Simple Example of a Sequence of Interrupt Requests with:
- Nested mode
- IEN unchanged by the interrupt routines
Priority Level of
Interrupt Request
INTERRUPT 0 HAS PRIORITY LEVEL 0
INTERRUPT 2 HAS PRIORITY LEVEL 2
INTERRUPT 3 HAS PRIORITY LEVEL 3
INTERRUPT 4 HAS PRIORITY LEVEL 4
INTERRUPT 5 HAS PRIORITY LEVEL 5
INTERRUPT 6 HAS PRIORITY LEVEL 6
INT 0
CPL=0
0
1
2
3
4
CPL6 > CPL3:
INT6 pending
INT0
INT 2
CPL=2
INT 2
CPL=2
INT6
INT 3
INT2
CPL=3
INT2
INT3
INT4
INT 4
CPL=4
CPL2 < CPL4:
Serviced next
5
INT 5
CPL=5
ei
6
INT 6
CPL=6
INT5
7
MAIN
CPL is set to 7
MAIN
CPL=7
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STMICROELECTRONICS [ ST ]
