Register set
ST10F276E
xxIC (yyyyh / zzh)
SFR area
8
Reset value: --00h
15
-
14
-
13
-
12
-
11
-
10
-
9
-
7
6
5
4
3
2
1
0
-
xxIR xxIE
RW RW
ILVL
RW
GLVL
RW
Table 83. SFR area description
Bit
Function
Group level
Defines the internal order for simultaneous requests of the same priority.
3: Highest group priority
0: Lowest group priority
GLVL
ILVL
Interrupt priority level
Defines the priority level for the arbitration of requests.
Fh: Highest priority level
0h: Lowest priority level
Interrupt enable control bit (individually enables/disables a specific source)
xxIE
xxIR
0: Interrupt request is disabled
1: Interrupt request is enabled
Interrupt request flag
0: No request pending
1: This source has raised an interrupt request
XPERCON (F024h / 12h)
ESFR
8
Reset value:- 005h
15
-
14
-
13
-
12
-
11
-
10
9
7
6
5
4
3
2
1
0
XMISC XI2C XSSC XASC XPWM XFLAS XRTC XRAM2 XRAM1 CAN2 CAN1
EN EN EN EN EN HEN EN EN EN EN EN
-
-
-
-
-
RW RW RW RW RW RW RW RW RW RW RW
Table 84. ESFR description
Bit
Function
CAN1 enable bit
0: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled (P4.5
and P4.6 pins can be used as general purpose I/Os, but address range 00’EC00h-
00’EFFFh is directed to external memory only if CAN2EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN an XMISCEN are ‘0’ also).
CAN1EN
1: The on-chip CAN1 XPeripheral is enabled and can be accessed.
CAN2 enable bit
0: Accesses to the on-chip CAN2 XPeripheral and its functions are disabled (P4.4
and P4.7 pins can be used as general purpose I/Os, but address range 00’EC00h-
00’EFFFh is directed to external memory only if CAN1EN, XRTCEN, XASCEN,
XSSCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also).
CAN2EN
1: The on-chip CAN2 XPeripheral is enabled and can be accessed.
XRAM1 enable bit
0: Accesses to the on-chip 2 Kbyte XRAM are disabled. Address range 00’E000h-
00’E7FFh is directed to external memory.
XRAM1EN
1: The on-chip 2 Kbyte XRAM is enabled and can be accessed.
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
