Register set
ST10F276E
Table 77. SYSCON description (continued)
Bit
Function
Write configuration control (inverted copy of WRC bit of RP0H)
WRCFG
CLKEN
BYTDIS
ROMEN
SGTDIS
0: Pins WR and BHE retain their normal function.
1: Pin WR acts as WRL, pin BHE acts as WRH.
System clock output enable (CLKOUT)
0: CLKOUT disabled, pin may be used for general purpose I/O.
1: CLKOUT enabled, pin outputs the system clock signal or a prescaled value of
system clock according to XCLKOUTDIV register setting.
Disable/enable control for pin BHE (set according to data bus width)
0: Pin BHE enabled.
1: Pin BHE disabled, pin may be used for general purpose I/O.
Internal memory enable (set according to pin EA during reset)
0: Internal memory disabled: Accesses to the IFlash Memory area use the
external bus.
1: Internal memory enabled.
Segmentation disable/enable control
0: Segmentation enabled (CSP is saved/restored during interrupt entry/exit).
1: Segmentation disabled (Only IP is saved/restored).
Internal memory mapping
ROMS1
STKSZ
0: Internal memory area mapped to segment 0 (00’0000h...00’7FFFh).
1: Internal memory area mapped to segment 1 (01’0000h...01’7FFFh).
System stack size
Selects the size of the system stack (in the internal I-RAM) from 32 to 1024 words.
BUSCON0 (FF0Ch / 86h)
15 14 13
SFR
Reset value: 0xx0h
12
11
10
9
8
7
7
7
7
6
6
6
6
5
4
3
2
1
0
CSWEN0CSREN0 RDYPOL0 RDYEN0
-
BUSACT0 ALECTL0
-
BTYP
MTTC0 RWDC0
MCTC
RW
RW
RW
RW
RW
RW
RW RW
RW
BUSCON1 (FF14h / 8Ah)
15 14 13
SFR
Reset value: 0000h
12
11
10
9
8
5
4
3
2
1
0
CSWEN1CSREN1 RDYPOL1 RDYEN1
-
BUSACT1 ALECTL1
-
BTYP
MTTC1 RWDC1
MCTC
RW
RW
RW
RW
RW
RW
RW
RW RW
RW
BUSCON2 (FF16h / 8Bh)
15 14 13
SFR
Reset value: 0000h
12
11
10
9
8
5
4
3
2
1
0
CSWEN2CSREN2 RDYPOL2 RDYEN2
-
BUSACT2 ALECTL2
-
BTYP
MTTC2 RWDC2
MCTC
RW
RW
RW
RW
RW
RW
RW RW
RW
BUSCON3 (FF18h / 8Ch)
15 14 13
SFR
Reset value: 0000h
12
11
10
9
8
5
4
3
2
1
0
CSWEN3CSREN3 RDYPOL3 RDYEN3
-
BUSACT3 ALECTL3
-
BTYP
MTTC3 RWDC3
MCTC
RW
RW
RW
RW
RW
RW
RW RW
RW
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Doc ID 12303 Rev 3
STMICROELECTRONICS [ ST ]
