M25PE10, M25PE20
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
These values are specified in Table 7.
If the delay, t , has elapsed, after V has risen
VSL
CC
the voltage applied on V ) until V reaches the
CC
CC
above V (min), the device can be selected for
CC
correct value:
READ instructions even if the t
fully elapsed.
delay is not yet
PUW
–
V
(min) at Power-up, and then for a further
CC
delay of t
VSL
As an extra protection, the Reset (Reset) signal
could be driven Low for the whole duration of the
Power-up and Power-down phases.
–
V
at Power-down
SS
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
At Power-up, the device is in the following state:
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
–
The device is in the Standby Power mode (not
the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
–
vice is held reset while V is less than the Power
CC
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC supply. Each de-
vice in a system should have the VCC rail decou-
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1 µF).
On Reset (POR) threshold value, V – all opera-
tions are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
WI
At Power-down, when VCC drops from the operat-
ing voltage, to below the Power On Reset (POR)
threshold voltage, VWI, all operations are disabled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
tions until a time delay of t
has elapsed after
PUW
the moment that V rises above the V thresh-
CC
WI
old. However, the correct operation of the device
is not guaranteed if, by this time, V is still below
CC
V
(min). No Write, Program or Erase instructions
CC
should be sent until the later of:
–
–
t
t
after V passed the V threshold
CC WI
PUW
VSL
after V passed the V (min) level
CC
CC
Figure 20. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
24/37
STMICROELECTRONICS [ ST ]
