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M25PE10-VMN6TG 参数 Datasheet PDF下载

M25PE10-VMN6TG图片预览
型号: M25PE10-VMN6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆位,低电压,页面可擦除串行闪存产品与字节变性, 33兆赫的SPI总线,标准引脚输出 [1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 37 页 / 483 K
品牌: STMICROELECTRONICS [ ST ]
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M25PE10, M25PE20  
Deep Power-down (DP)  
Executing the Deep Power-down (DP) instruction  
is the only way to put the device in the lowest con-  
sumption mode (the Deep Power-down mode). It  
can also be used as an extra software protection  
mechanism, while the device is not in active use,  
since in this mode, the device ignores all Write,  
Program and Erase instructions.  
The Deep Power-down mode automatically stops  
at Power-down, and the device always Powers-up  
in Standby Power mode.  
The Deep Power-down (DP) instruction is entered  
by driving Chip Select (S) Low, followed by the in-  
struction code on Serial Data Input (D). Chip Se-  
lect (S) must be driven Low for the entire duration  
of the sequence.  
Driving Chip Select (S) High deselects the device,  
and puts the device in Standby Power mode (if  
there is no internal cycle currently in progress). But  
this mode is not the Deep Power-down mode. The  
Deep Power-down mode can only be entered by  
executing the Deep Power-down (DP) instruction,  
subsequently reducing the standby current (from  
The instruction sequence is shown in Figure 18.  
Chip Select (S) must be driven High after the  
eighth bit of the instruction code has been latched  
in, otherwise the Deep Power-down (DP) instruc-  
tion is not executed. As soon as Chip Select (S) is  
driven High, it requires a delay of t before the  
DP  
supply current is reduced to I  
Power-down mode is entered.  
and the Deep  
CC2  
I
to I  
, as specified in Table 12.).  
CC1  
CC2  
Once the device has entered the Deep Power-  
down mode, all instructions are ignored except the  
Release from Deep Power-down (RDP) instruc-  
tion. This releases the device from this mode.  
Any Deep Power-down (DP) instruction, while an  
Erase, Program or Write cycle is in progress, is re-  
jected without having any effects on the cycle that  
is in progress.  
Figure 18. Deep Power-down (DP) Instruction Sequence  
S
tDP  
0
1
2
3
4
5
6
7
C
D
Instruction  
Standby Power Mode  
Deep Power-down Mode  
AI03753D  
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