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M25PE10-VMN6TG 参数 Datasheet PDF下载

M25PE10-VMN6TG图片预览
型号: M25PE10-VMN6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆位,低电压,页面可擦除串行闪存产品与字节变性, 33兆赫的SPI总线,标准引脚输出 [1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 37 页 / 483 K
品牌: STMICROELECTRONICS [ ST ]
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M25PE10, M25PE20  
Release from Deep Power-down (RDP)  
High. Sending additional clock cycles on Serial  
Clock (C), while Chip Select (S) is driven Low,  
cause the instruction to be rejected, and not exe-  
cuted.  
Once the device has entered the Deep Power-  
down mode, all instructions are ignored except the  
Release from Deep Power-down (RDP) instruc-  
tion. Executing this instruction takes the device out  
of the Deep Power-down mode.  
After Chip Select (S) has been driven High,  
followed by a delay, t  
, the device is put in  
RDP  
Standby Power mode. Chip Select (S) must  
remain High at least until this period is over. The  
device waits to be selected, so that it can receive,  
decode and execute instructions.  
Any Release from Deep Power-down (RDP) in-  
struction, while an Erase, Program or Write cycle  
is in progress, is rejected without having any ef-  
fects on the cycle that is in progress.  
The Release from Deep Power-down (RDP) in-  
struction is entered by driving Chip Select (S) Low,  
followed by the instruction code on Serial Data In-  
put (D). Chip Select (S) must be driven Low for the  
entire duration of the sequence.  
The instruction sequence is shown in Figure 19.  
The Release from Deep Power-down (RDP) in-  
struction is terminated by driving Chip Select (S)  
Figure 19. Release from Deep Power-down (RDP) Instruction Sequence  
S
tRDP  
0
1
2
3
4
5
6
7
C
D
Instruction  
High Impedance  
Q
Deep Power-down Mode  
Standby Power Mode  
AI06807  
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