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M25PE10-VMN6TG 参数 Datasheet PDF下载

M25PE10-VMN6TG图片预览
型号: M25PE10-VMN6TG
PDF下载: 下载PDF文件 查看货源
内容描述: 1和2兆位,低电压,页面可擦除串行闪存产品与字节变性, 33兆赫的SPI总线,标准引脚输出 [1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out]
分类和应用: 闪存存储内存集成电路光电二极管时钟
文件页数/大小: 37 页 / 483 K
品牌: STMICROELECTRONICS [ ST ]
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M25PE10, M25PE20  
Table 13. AC Characteristics (25MHz operation)  
Test conditions specified in Table 9. and Table 10.  
Symbol  
Alt.  
Parameter  
Min.  
Typ.  
Max.  
Unit  
Clock Frequency for the following  
instructions: FAST_READ, PW, PP,  
PE, SE, DP, RDP, WREN, WRDI,  
RDSR  
f
f
D.C.  
25  
MHz  
C
C
Clock Frequency for READ  
instructions  
f
D.C.  
20  
MHz  
R
(1)  
t
Clock High Time  
Clock Low Time  
18  
18  
ns  
ns  
t
CLH  
CH  
(1)  
t
t
CLL  
CL  
2
0.1  
10  
10  
5
V/ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
µs  
Clock Slew Rate (peak to peak)  
t
t
t
t
t
S Active Setup Time (relative to C)  
S Not Active Hold Time (relative to C)  
Data In Setup Time  
SLCH  
CHSL  
CSS  
DVCH  
CHDX  
CHSH  
SHCH  
DSU  
t
t
t
t
Data In Hold Time  
5
DH  
S Active Hold Time (relative to C)  
S Not Active Setup Time (relative to C)  
S Deselect Time  
10  
10  
200  
t
t
CSH  
SHSL  
(2)  
t
Output Disable Time  
15  
15  
t
DIS  
SHQZ  
t
t
V
Clock Low to Output Valid  
Output Hold Time  
CLQV  
t
t
HO  
0
CLQX  
t
t
Top Sector Lock Setup Time  
Top Sector Lock Hold Time  
S to Deep Power-down  
50  
THSL  
100  
SHTL  
(2)  
3
t
DP  
(2)  
(3)  
S High to Standby Power Mode  
30  
µs  
t
RDP  
Page Write Cycle Time (256 Bytes)  
11  
25  
5
ms  
t
PW  
10.2 +  
n*0.8/256  
Page Write Cycle Time (n Bytes)  
Page Program Cycle Time (256 Bytes)  
Page Program Cycle Time (n Bytes)  
1.2  
(3)  
ms  
t
PP  
0.4 +  
n*0.8/256  
t
Page Erase Cycle Time  
Sector Erase Cycle Time  
10  
1
20  
5
ms  
s
PE  
t
SE  
Note: 1. t + t must be greater than or equal to 1/ f  
C
CH  
CL  
2. Value guaranteed by characterization, not 100% tested in production.  
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all  
the Bytes versus several sequences of only a few Bytes. (1 n 256)  
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