M25PE10, M25PE20
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all
bits inside the chosen page. Before it can be ac-
cepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write
Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Page Erase (PE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address Bytes on Serial
Data Input (D). Any address inside the Page is a
valid address for the Page Erase (PE) instruction.
Chip Select (S) must be driven Low for the entire
duration of the sequence.
latched in, otherwise the Page Erase (PE) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, the self-timed Page Erase cycle
(whose duration is t ) is initiated. While the Page
PE
Erase cycle is in progress, the Status Register
may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Page Erase cycle, and
is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Erase (PE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
Figure 16. Page Erase (PE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI04046
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
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STMICROELECTRONICS [ ST ]
