16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
Data Sheet
T
T
AA
RC
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
CHZ
T
OH
T
HIGH-Z
CLZ
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
523 ILL F04.0
FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
19-0
T
AH
T
WP
WE#
T
T
AS
WPH
OE#
BEF#
T
CH
T
CS
T
BR
T
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
SW0
XX55
SW1
XXA0
SW2
DATA
VALID
WORD
(ADDR/DATA)
523 ILL F05.3
Note: X can be V or V , but no other value.
IL
IH
FIGURE 7: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71172-05-000 10/01 523
18