16 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory
SST34HF1621 / SST34HF1641
Data Sheet
ADDRESS A
19-0
T
CE
BEF#
OE#
T
T
OE
OEH
WE#
T
BR
VALID DATA
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
523 ILL F08.2
FIGURE 10: FLASH TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
SW0
XX55
SW1
XX80
SW2
XXAA
SW3
XX55
SW4
XX10
SW5
VALID
523 ILL F09.5
Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF#
signals are interchageable as long as minimum timings are met. (See Table 15)
X can be V or V , but no other value.
IL IH
FIGURE 11: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71172-05-000 10/01 523
20
SST [ SILICON STORAGE TECHNOLOGY, INC ]
