16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1602C / SST34HF1622C / SST34HF1642C
SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S
Advance Information
T
WCS
3
ADDRESSES A
MSS -0
T
T
WRS
WPS
WE#
T
BWS
BES1#
BES2
T
BWS
T
AWS
T
ASTS
T
BYWS
UBS#, LBS#
T
T
DHS
DSS
DQ
DQ
7-0
15-8,
NOTE 2
NOTE 2
VALID DATA IN
1256 F06.0
Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
3. AMSS = Most Significant SRAM Address
AMSS = A16 for SST34HF1622C, A17 for SST34HF1622C/D, and A18 for SST34HF1682D
FIGURE 7: (P)SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 X16 (P)SRAM ONLY
©2004 Silicon Storage Technology, Inc.
S71256-00-000
3/04
21
SST [ SILICON STORAGE TECHNOLOGY, INC ]
