16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1602C / SST34HF1622C / SST34HF1642C
SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S
Advance Information
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
5555 5555 2AAA
ADDRESS A
19-0
5555
2AAA
BA
X
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
1256 F13.0
Note: This device also supports BEF# controlled Block-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
BAX = Block Address
X can be VIL or VIH, but no other value.
FIGURE 14: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DON’T CARE)
SIX-BYTE CODE FOR SECTOR-ERASE
2AAA 5555 5555 2AAA
T
SE
5555
SA
X
ADDRESS A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
1256 F14.0
Note: This device also supports BEF# controlled Sector-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
SAX = Sector Address
X can be VIL or VIH, but no other value.
FIGURE 15: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DON’T CARE)
©2004 Silicon Storage Technology, Inc.
S71256-00-000
3/04
25
SST [ SILICON STORAGE TECHNOLOGY, INC ]
