16 Mbit Concurrent SuperFlash + 2/4/8 Mbit SRAM ComboMemory
SST34HF1602C / SST34HF1622C / SST34HF1642C
SST34HF1642D / SST34HF1682D / SST34HF1622S / SST34HF1642S
Advance Information
ADDRESS A
19-0
T
CE
BEF#
OE#
T
OEH
T
OE
WE#
T
BR
VALID DATA
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
1256 F11.0
FIGURE 12: FLASH TOGGLE BIT TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DON’T CARE)
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
5555
2AAA
5555
5555
2AAA
5555
ADDRESS A
19-0
BEF#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
DQ
15-0
XXAA
XX55
XX80
XXAA
XX55
XX10
VALID
1256 F12.0
Note: This device also supports BEF# controlled Chip-Erase operation.
The WE# and BEF# signals are interchangeable as long as minimum timings are meet. (See Table 15.)
X can be VIL or VIH, but no other value.
FIGURE 13: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM FOR WORD MODE
(FOR BYTE MODE A-1 = DON’T CARE)
©2004 Silicon Storage Technology, Inc.
S71256-00-000
3/04
24
SST [ SILICON STORAGE TECHNOLOGY, INC ]
