1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Instructions
Instructions are used to read, write (erase and program), and configure the SST26WF032. The
instruction bus cycles are two nibbles each for commands (Op Code), data, and addresses. Prior to
executing any write instructions, the Write-Enable (WREN) instruction must be executed. The com-
plete list of the instructions is provided in Table 3.
All instructions are synchronized off a high to low transition of CE#. Inputs are accepted on the rising
edge of SCK starting with the most significant nibble. CE# must be driven low before an instruction is
entered and must be driven high after the last nibble of the instruction has been input (except for read
instructions). Any low-to-high transition on CE# before receiving the last nibble of an instruction bus
cycle, will terminate the instruction being entered and return the device to the standby mode.
Table 3: Device Operation Instructions for SST26WF032
Command
Cycle1
Address
Cycle(s)2
Dummy
Cycle(s)
Data
Maximum
Frequency
Instruction
NOP
Description
Cycle(s)
No Operation
Reset Enable
Reset Memory
Enable Quad I/O
Reset Quad I/O
Read Memory
00H
66H
99H
38H
FFH
03H
0BH
0
0
0
0
0
3
3
0
0
0
0
0
0
2
0
RSTEN
RST3
0
0
0
80 MHz
25 MHz
EQIO
RSTQIO4
Read5
High-Speed Read5 Read Memory at
Higher Speed
0
1 to ∞
1 to ∞
Set Burst6
Set Burst Length
nB Burst with Wrap
JEDEC-ID Read
C0H
0CH
9FH
AFH
20H
0
3
0
0
3
0
2
0
0
0
1
Read Burst
JEDEC-ID 5,7
Quad J-ID7
Sector Erase8
n to ∞
3 to ∞
3 to ∞
0
Quad I/O J-ID Read
Erase 4 KBytes of
Memory Array
Block Erase9
Erase 64, 32 or 8
KBytes of Memory
Array
D8H
3
0
0
Chip Erase
Erase Full Array
C7H
02H
0
3
0
0
0
Page Program
Program 1 to 256
Data Bytes
1 to 256
80 MHz
Write Suspend
Write Resume
Suspends Program/
Erase
B0H
30H
0
0
0
0
0
0
Resumes Program/
Erase
Read SID
Program SID10
Read Security ID
88H
A5H
1
1
2
0
1 to 32
1 to 24
Program User Secu-
rity ID area
Lockout SID10
RDSR11
Lockout Security ID
Programming
85H
05H
06H
0
0
0
0
0
0
0
1 to ∞
0
Read Status Regis-
ter
WREN
Write Enable
©2010 Silicon Storage Technology, Inc.
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