CY28412
Byte 6: Control Register 6
Bit
7
@Pup
Name
Description
0
0
RESERVED
RESERVED, Set = 0
6
Test Clock Mode Entry Control
1 = Hi-Z mode, 0 = Normal operation
5
4
3
1
1
1
REF1
REF0
REF1 Output Drive Strength
0 = Low, 1 = High
REF0 Output Drive Strength
0 = Low, 1 = High
PCIF, SRC, PCI
SW PCI_STP# Function
0=SW PCI_STP assert, 1= SW PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
Externally
selected
CPUT/C
CPUT/C
CPUT/C
FS_C. Reflects the value of the FS_C pin sampled on power up
0 = FS_C was low during VTT_PWRGD# assertion
Externally
selected
FS_B. Reflects the value of the FS_B pin sampled on power up
0 = FS_B was low during VTT_PWRGD# assertion
Externally
selected
FS_A. Reflects the value of the FS_A pin sampled on power up
0 = FS_A was low during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
7
@Pup
Name
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
0
0
1
0
1
0
0
0
6
5
4
3
2
Vendor ID Bit 2
Vendor ID Bit 2
1
Vendor ID Bit 1
Vendor ID Bit 1
0
Vendor ID Bit 0
Vendor ID Bit 0
Crystal Recommendations
Crystal Loading
The CY28412 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28412 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the
following discussion is that the trim capacitors are in series
with the crystal not parallel. It’s a common misconception that
load capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Table 5. Crystal Recommendations
Frequency
(Fund)
Drive
(max.)
Shunt Cap Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
Cut
Loading Load Cap
Parallel 20 pF
(max.)
14.31818 MHz
AT
0.1 mW
5 pF
0.016 pF
50 ppm
50 ppm
5 ppm
Rev 1.0,November 20, 2006
Page 7 of 16
SPECTRALINEAR [ SPECTRALINEAR INC ]
