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CY28412OCT 参数 Datasheet PDF下载

CY28412OCT图片预览
型号: CY28412OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢的Grantsdale芯片组 [Clock Generator for Intel㈢ Grantsdale Chipset]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 205 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28412  
Byte 1: Control Register 1  
Bit  
@Pup  
Name  
Description  
7
1
CPUT/C  
SRCT/C  
PCIF  
Center Spread Enable  
0 = 0.25% Center Spread, 1 = –0.5% Down Spread  
PCI  
6
5
4
3
2
1
0
1
1
1
1
1
1
0
DOT_96T/C  
USB_48  
REF0  
DOT_96 MHz Output Enable  
0 = Disable (Hi-Z), 1 = Enabled  
USB_48 MHz Output Enable  
0 = Disabled, 1 = Enabled  
REF0 Output Enable  
0 = Disabled, 1 = Enabled  
REF1  
REF1 Output Enable  
0 = Disabled, 1 = Enabled  
CPU[T/C]1  
CPU[T/C]0  
CPU[T/C]1 Output Enable  
0 = Disable (Hi-Z), 1 = Enabled  
CPU[T/C]0 Output Enable  
0 = Disable (Hi-Z), 1 = Enabled  
CPUT/C  
SRCT/C  
PCIF  
Spread Spectrum Enable  
0 = Spread off, 1 = Spread on  
PCI  
Byte 2: Control Register 2  
Bit  
@Pup  
Name  
Description  
7
1
PCI5  
PCI5 Output Enable  
0 = Disabled, 1 = Enabled  
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PCI4  
PCI3  
PCI2  
PCI1  
PCI0  
PCIF1  
PCIF0  
PCI4 Output Enable  
0 = Disabled, 1 = Enabled  
PCI3 Output Enable  
0 = Disabled, 1 = Enabled  
PCI2 Output Enable  
0 = Disabled, 1 = Enabled  
PCI1 Output Enable  
0 = Disabled, 1 = Enabled  
PCI0 Output Enable  
0 = Disabled, 1 = Enabled  
PCIF1 Output Enable  
0 = Disabled, 1 = Enabled  
PCIF0 Output Enable  
0 = Disabled, 1 = Enabled  
Byte 3: Control Register 3  
Bit  
@Pup  
Name  
Description  
7
0
CPUT2_ITP/SRCT6  
CPUC2_ITP/SRCC6  
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#  
0 = Free-running, 1 = Stopped with SW PCI_STP#  
6
5
4
3
0
0
0
0
SRC[T/C]5  
SRC[T/C]4  
SRC[T/C]3  
SATA[T/C]  
Allow control of SRC[T/C]5with assertion of SW PCI_STP#  
0 = Free-running, 1 = Stopped with SW PCI_STP#  
Allow control of SRC[T/C]4 with assertion of SW PCI_STP#  
0 = Free-running, 1 = Stopped with SW PCI_STP#  
Allow control of SRC[T/C]3with assertion of SW PCI_STP#  
0 = Free-running, 1 = Stopped with SW PCI_STP#  
Allow control of SATA[T/C] with assertion of SW PCI_STP#  
0 = Free-running, 1 = Stopped with SW PCI_STP#  
Rev 1.0,November 20, 2006  
Page 5 of 16