CY28412
Byte 3: Control Register 3 (continued)
Bit
@Pup
Name
Description
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
1
0
0
0
SRC1
SRC0
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of SRC[T/C]0 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Byte 4: Control Register 4
Bit
7
@Pup
Name
Description
0
0
RESERVED
DOT96[T/C]
RESERVED, Set = 0
6
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Hi-Z
5
4
0
0
PCIF1
PCIF0
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free-running, 1 = Stopped with SW PCI_STP#
3
2
1
0
0
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED, Set = 0
RESERVED, Set = 1
RESERVED, Set = 1
RESERVED, Set = 1
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C]Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Hi-Z when PCI_STP#
asserted
6
5
4
3
0
0
0
0
RESERVED
RESERVED
RESERVED
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
SRC[T/C][6:0],SATA[T/C] SRC[T/C], SATA[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
2
1
0
0
0
0
CPU[T/C]2
CPU[T/C]1
CPU[T/C]0
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Rev 1.0,November 20, 2006
Page 6 of 16