CY28412
clock chip. All differential outputs stopped in a tristate condition
resulting from power down must be driven high in less than
300 Ps of PD deassertion to a voltage greater than 200 mV.
After the clock chip’s internal PLL is powered up and locked,
all outputs are enabled within a few clock cycles of each other.
PD Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
Clock Chip
Ci2
Ci1
Pin
3 to 6p
X2
X1
Cs2
Cs1
Trace
2.8pF
XTAL
Ce1
Ce2
Trim
33pF
Figure 2. Crystal Loading Example
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 3. Power-down Assertion Timing Waveform
Rev 1.0,November 20, 2006
Page 9 of 16
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