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CY28412OCT 参数 Datasheet PDF下载

CY28412OCT图片预览
型号: CY28412OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢的Grantsdale芯片组 [Clock Generator for Intel㈢ Grantsdale Chipset]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 205 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28412  
izes to their default setting upon power-up, and therefore use  
of this interface is optional. Clock device register changes are  
normally made upon system initialization, if any are required.  
The interface cannot be used during system operation for pow-  
er management functions.  
Frequency Select Pins (FS_A, FS_B and FS_C)  
Host clock frequency selection is achieved by applying the  
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to  
VTT_PWRGD# assertion (as seen by the clock synthesizer).  
Upon VTT_PWRGD# being sampled low by the clock chip  
(indicating processor VTT voltage is stable), the clock chip  
samples the FS_A, FS_B and FS_C input values. For all logic  
levels of FS_A, FS_B and FS_C VTT_PWRGD# employs a  
Data Protocol  
The clock driver serial protocol accepts byte write, byte read,  
block write, and block read operations from the controller. For  
block write/read operation, the bytes must be accessed in se-  
quential order from lowest to highest byte (most significant bit  
first) with the ability to stop after any complete byte has been  
transferred. For byte write and byte read operations, the sys-  
tem controller can access individually indexed bytes. The off-  
set of the indexed byte is encoded in the command code, as  
described in Table 2.  
one-shot functionality in that once  
a
valid low on  
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,  
FS_A, FS_B and FS_C transitions will be ignored, except in  
test mode.  
Serial Data Interface  
To enhance the flexibility and function of the clock synthesizer,  
a two-signal serial interface is provided. Through the Serial  
Data Interface, various device functions, such as individual  
clock output buffers, can be individually enabled or disabled.  
The registers associated with the Serial Data Interface initial-  
The block write and block read protocol is outlined in Table 3  
while Table 4 outlines the corresponding byte write and byte  
read protocol. The slave receiver address is 11010010 (D2h).  
Table 1. Frequency Select Table (FS_A, FS_B, FS_C)  
FS_C  
FS_B  
FS_A  
CPU  
SRC  
PCIF/PCI  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
33 MHz  
REF0  
DOT96  
96 MHz  
96 MHz  
96 MHz  
96 MHz  
96 MHz  
96 MHz  
96 MHz  
96 MHz  
USB  
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
100 MHz  
133 MHz  
166 MHz  
200 MHz  
266 MHz  
333 MHz  
400 MHz  
Reserved  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
100 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
14.318 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
48 MHz  
Table 2. Command Code Definition  
Bit  
Description  
7
0 = Block read or block write operation, 1 = Byte read or byte write operation  
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'  
Table 3. Block Read and Block Write Protocol  
Block Write Protocol  
Description  
Block Read Protocol  
Description  
Bit  
1
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write = 0  
2:8  
9
Slave address – 7 bits  
Write = 0  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits  
'00000000' stands for block operation  
11:18  
Command Code – 8 bits  
'00000000' stands for block operation  
19  
20:27  
28  
Acknowledge from slave  
Byte Count – 8 bits  
19  
20  
Acknowledge from slave  
Repeat start  
Acknowledge from slave  
Data byte 1 – 8 bits  
21:27  
28  
Slave address – 7 bits  
Read = 1  
29:36  
37  
Acknowledge from slave  
Data byte 2 – 8 bits  
29  
Acknowledge from slave  
Byte count from slave – 8 bits  
Acknowledge from master  
38:45  
46  
30:37  
38  
Acknowledge from slave  
Rev 1.0,November 20, 2006  
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