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CY28412OCT 参数 Datasheet PDF下载

CY28412OCT图片预览
型号: CY28412OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟发生器Intel㈢的Grantsdale芯片组 [Clock Generator for Intel㈢ Grantsdale Chipset]
分类和应用: 时钟发生器
文件页数/大小: 16 页 / 205 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28412  
Table 3. Block Read and Block Write Protocol (continued)  
Block Write Protocol  
Block Read Protocol  
Description  
Bit  
....  
....  
....  
....  
....  
....  
Description  
Bit  
39:46  
47  
......................  
Data byte from slave – 8 bits  
Acknowledge from master  
Data byte from slave – 8 bits  
Acknowledge from master  
Data byte N from slave – 8 bits  
Acknowledge from master  
Stop  
Data Byte (N – 1) – 8 bits  
Acknowledge from slave  
Data Byte N – 8 bits  
Acknowledge from slave  
Stop  
48:55  
56  
....  
....  
....  
Table 4. Byte Read and Byte Write Protocol  
Byte Write Protocol  
Byte Read Protocol  
Description  
Bit  
1
Description  
Bit  
1
Start  
Start  
2:8  
9
Slave address – 7 bits  
Write = 0  
2:8  
9
Slave address – 7 bits  
Write = 0  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
Command Code – 8 bits  
11:18  
Command Code – 8 bits  
11:18  
'100xxxxx' stands for byte operation, bits[6:0] of the  
command code represents the offset of the byte to  
be accessed  
'100xxxxx' stands for byte operation, bits[6:0] of  
the command code represents the offset of the  
byte to be accessed  
19  
20:27  
28  
Acknowledge from slave  
Data byte from master – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
Acknowledge from slave  
Repeat start  
21:27  
28  
Slave address – 7 bits  
Read = 1  
29  
29  
Acknowledge from slave  
Data byte from slave – 8 bits  
Acknowledge from master  
Stop  
30:37  
38  
39  
Control Registers  
Byte 0:Control Register 0  
Bit  
@Pup  
Name  
Description  
7
1
CPUT2_ITP/SRCT6  
CPUC2_ITP/SRCC6  
CPU[T/C]2_ITP/SRC[T/C]6 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]5  
SRC[T/C]4  
SRC[T/C]3  
SATAT/C]  
SRC[T/C]5 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
SRC[T/C]4 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
SRC[T/C]3 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
SATA[T/C] Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
SRC[T/C]2  
SRC[T/C]1  
SRC[T/C]0  
SRC[T/C]2 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
SRC[T/C]1 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
SRC[T/C]0 Output Enable  
0 = Disable (Hi-Z), 1 = Enable  
Rev 1.0,November 20, 2006  
Page 4 of 16