CY28346-2
Pin Description
Pin
Name
PWR
VDD
VDD
I/O
I
Description
2
3
XIN
XOUT
Oscillator Buffer Input. Connect to a crystal or to an external clock.
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
52, 51, 49, 48, CPUT(0:2),
45, 44 CPUC(0:2)
VDD
VDDP
VDD
O
O
O
Differential host output clock pairs. See Table 1 for frequencies and
functionality.
10, 11, 12, 13, PCI(0:6)
16, 17, 18
PCI clock outputs. Are synchronous to 66IN or 3V66 clock. See Table 1.
5, 6, 7
PCIF (0:2)
33-MHz PCI clocks, which are y2 copies of 66IN or 3V66 clocks, may
be free running (not stopped when PCI_STP# is asserted LOW) or
may be stoppable depending on the programming of SMBus
register Byte3, Bits (3:5).
56
42
REF
VDD
VDD
O
I
Buffered output copy of the device’s XIN clock.
IREF
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF.
28
VTT_PWRGD#
VDD
I
Qualifying input that latches S(0:2) and MULT0. When this input is at
a logic low, the S(0:2) and MULT0 are latched.
39
38
33
35
48M_USB
48M_DOT
3V66_0
VDD48
VDD48
VDD
O
O
O
O
Fixed 48-MHz USB clock outputs.
Fixed 48-MHZ DOT clock outputs.
3.3V 66-MHz fixed frequency clock.
3V66_1/VCH
VDD
3.3V clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.
When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock. When
byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
25
43
PD#
VDD
VDD
I
This pin is a power-down mode pin. A logic LOW level causes the
PU device to enter a power-down state. All internal logic is turned off except
for the SMBus logic. All output buffers are stopped.
MULT0
I
PU
Programming input selection for CPU clock current multiplier.
55, 54
29
S(0,1)
I
I
I
I
Frequency select inputs. See Table 1
SDATA
Serial data input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open
drain output when acknowledging or transmitting data.
30
40
SCLK
S2
I
I
Serial clock input. Conforms to the SMBus specification.
VDD
I
T
Frequency select input. See Table 1. This is a Tri-level input that is
driven HIGH, LOW, or driven to a intermediate level.
34
PCI_STP#
VDD
VDD
I
PCI clock disable input. When asserted LOW, PCI (0:6) clocks are
PU synchronously disabled in a LOW state. This pin does not effect PCIF
(0:2) clocks’ outputs if they are programmed to be PCIF clocks via the
device’s SMBus interface.
53
CPU_STP#
I
CPU clock disable input. When asserted LOW, CPUT (0:2) clocks are
PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are
synchronously disabled in a LOW state.
24
66IN/3V66_5
VDD
VDD
–
I/O Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or
output clock for fixed 66-MHz clock if S2 = 0. See Table 1.
21, 22, 23
66B(0:2)/
3V66(2:4)
O
3.3V clock outputs. These clocks are buffered copies of the 66IN clock
or fixed at 66 MHz. See Table 1.
1, 8, 14, 19, 32, VDD
37, 46, 50
PWR 3.3V power supply.
PWR Common ground.
4, 9, 15, 20, 27, VSS
31, 36, 47
–
Rev 1.0,November 20, 2006
Page 2 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
