A d v a n c e I n f o r m a t i o n
Command Definitions
Writing specific address and data commands or sequences into the command
register initiates device operations. Tables 19-20 define the valid register com-
mand sequences. Writing incorrect address and data values or writing them
in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens
later. All data is latched on the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data in Non-burst Mode
The device is automatically set to reading array data after device power-up. No
commands are required to retrieve data. The device is also ready to read array
data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase
Suspend mode. The system can read array data using the standard read timings,
except that if it reads at an address within erase-suspended sectors, the device
outputs status data. After completing a programming operation in the Erase Sus-
pend mode, the system may once again read array data with the same exception.
See Sector Erase and Program Suspend Command for more information on this
mode.
The system must issue the reset command to re-enable the device for reading
array data if DQ5 goes high, or while in the autoselect mode. See the The pro-
gramming of the PPB Lock Bit for a given sector can be verified by writing a PPB
Lock Bit status verify command to the device. section.
See also Asynchronous Read Operation (Non-Burst) in the Key to Switching Wave-
forms section for more information. See the Sector Erase and Program Resume
Command sections for more information on this mode.
Reading Array Data in Burst Mode
The device is capable of very fast Burst mode read operations. The configuration
register sets the read configuration, burst order, frequency configuration, and
burst length.
Upon power on, the device defaults to the asynchronous mode. In this mode,
CLK, and ADV# are ignored. The device operates like a conventional Flash device.
Data is available t
/t nanoseconds after address becomes stable, CE# be-
ACC CE
come asserted. The device enters the burst mode by enabling synchronous burst
reads in the configuration register. The device exits burst mode by disabling syn-
chronous burst reads in the configuration register. (See Command Definitions).
The RESET# command will not terminate the Burst mode. System reset (power
on reset) will terminate the Burst mode.
The device has the regular control pins, i.e. Chip Enable (CE#), Write Enable
(WE#), and Output Enable (OE#) to control normal read and write operations.
Moreover, three additional control pins have been added to allow easy interface
with minimal glue logic to a wide range of microprocessors / microcontrollers for
high performance Burst read capability. These additional pins are Address Valid
(ADV#) and Clock (CLK). CE#, OE#, and WE# are asynchronous (relative to
CLK). The Burst mode read operation is a synchronous operation tied to the edge
of the clock. The microprocessor / microcontroller supplies only the initial ad-
dress, all subsequent addresses are automatically generated by the device with
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S29CD032G
30606B0 March 22, 2004
SPANSION [ SPANSION ]
