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S25FL040A0LVFI001 参数 Datasheet PDF下载

S25FL040A0LVFI001图片预览
型号: S25FL040A0LVFI001
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位CMOS 3.0伏闪存与50MHz的SPI (串行外设接口)总线和小部门的引导和参数存储 [4 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus and Small Sector for Boot and Parameter Storage]
分类和应用: 闪存存储
文件页数/大小: 35 页 / 1040 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.12 Deep Power Down (DP) Command Sequence  
CS#  
SCK  
t
DP  
0
1
2
3
4
5
6
7
Mode 3  
Mode 0  
Command  
SI  
Hi-Z  
SO  
Standby Mode  
Deep Power-down Mode  
9.13 Release from Deep Power Down (RES)  
The device requires the Release from Deep Power Down (RES) command to exit the Deep Power Down  
mode. When the device is in the Deep Power Down mode, all commands except RES are ignored.  
The host system must drive CS# low and write the RES command to SI. CS# must be driven low for the entire  
duration of the sequence. The command sequence is shown in Figure 9.13 and Table 9.5.  
The host system must drive CS# high tRES(max) after the 8-bit RES command byte. The device transitions  
from DP mode to the standby mode after a delay of tRES (see Table 16.1 on page 27). In the standby mode,  
the device can execute any read or write command.  
Figure 9.13 Release from Deep Power Down (RES) Command Sequence  
CS#  
7
0
2
3
5
1
4
6
Mode 3  
SCK  
Mode 0  
tRES  
Command  
SI  
Hi-Z  
SO  
Deep Power-down Mode  
Standby Mode  
9.13.1  
Release from Deep Power Down and Read Electronic Signature (RES)  
The device features an 8-bit Electronic Signature, which can be read using the RES command. See  
Figure 9.14 and Table 9.5 for the command sequence and signature value. The Electronic Signature is not to  
be confused with the identification data obtained using the RDID command. The device offers the Electronic  
Signature so that it can be used with previous devices that offered it; however, the Electronic Signature  
should not be used for new designs, which should read the RDID data instead.  
After the host system drives CS# low, it must write the RES command followed by 3 dummy bytes to SI (each  
bit is latched on SI during the rising edge of SCK). The Electronic Signature is then output on SO; each bit is  
shifted out on the falling edge of SCK. The RES operation is terminated by driving CS# high after the  
Electronic Signature is read at least once. Additional clock cycles on SCK with CS# low cause the device to  
output the Electronic Signature repeatedly.  
August 31, 2006 S25FL040A_00_B0  
S25FL040A  
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