D a t a S h e e t ( P r e l i m i n a r y )
A pull-up resistor on Chip Select (CS#) typically meets proper power-up and power-down requirements.
No Write Status Register, program, or erase command should be sent to the device until VCC rises to the VCC
min, plus a delay of tPU. At power-up, the device is in standby mode (not Deep Power Down mode) and the
WEL bit is reset (0).
Each device in the host system should have the VCC rail decoupled by a suitable capacitor close to the
package pins (this capacitor is generally of the order of 0.1 µF), as a precaution to stabilizing the VCC feed.
When VCC drops from the operating voltage to below the minimum VCC threshold at power-down, all
operations are disabled and the device does not respond to any commands. Note that data corruption may
result if a power-down occurs while a Write Register, program, or erase operation is in progress.
Figure 10.1 Power-Up Timing Diagram
Vcc
(max)
cc
V
(min)
cc
V
tPU
Full Device Access
Time
Table 10.1 Power-Up Timing Characteristics
Symbol
Parameter
Min
2.7
10
Max
Unit
V
V
V
(minimum)
CC(min)
CC
t
V
(min) to device operation
CC
ms
PU
11. Initial Delivery State
The device is delivered with all bits set to 1 (each byte contains FFh) upon initial factory shipment. The Status
Register contains 00h (all Status Register bits are 0).
12. Absolute Maximum Ratings
Do not stress the device beyond the ratings listed in this section, or serious, permanent damage to the device
may result. These are stress ratings only and device operation at these or any other conditions beyond those
indicated in this section and in the Operating Ranges section of this document is not implied. Device
operation for extended periods at the limits listed in this section may affect device reliability.
Table 12.1 Absolute Maximum Ratings
Description
Ambient Storage Temperature
Voltage with Respect to Ground: All Inputs and I/Os
Rating
–65°C to +150°C
–0.3 V to 4.5 V
August 31, 2006 S25FL040A_00_B0
S25FL040A
25
SPANSION [ SPANSION ]
