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S25FL040A0LVFI001 参数 Datasheet PDF下载

S25FL040A0LVFI001图片预览
型号: S25FL040A0LVFI001
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位CMOS 3.0伏闪存与50MHz的SPI (串行外设接口)总线和小部门的引导和参数存储 [4 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus and Small Sector for Boot and Parameter Storage]
分类和应用: 闪存存储
文件页数/大小: 35 页 / 1040 K
品牌: SPANSION [ SPANSION ]
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D a t a S h e e t ( P r e l i m i n a r y )  
Figure 9.8 Write Status Register (WRSR) Command Sequence  
CS#  
SCK  
8
9
10  
12 13 14 15  
11  
4
6
7
Mode 3  
0
1
2
3
5
Mode 0  
Command  
Register In  
Status  
7
6
5
4
3
2
1
0
SI  
MSB  
Hi-Z  
SO  
Table 9.4 Protection Modes  
Protected Area  
(See Note)  
Unprotected Area  
(See Note)  
W# Signal  
SRWD Bit  
Mode  
Write Protection of the Status Register  
1
1
0
1
0
0
Status Register is writable (if the WREN  
command has set the WEL bit). The values in  
the SRWD, BP2, BP1 and BP0 bits can be  
changed.  
Software  
Protected  
(SPM)  
Ready to accept Page  
Program and Sector Erase  
commands  
Protected against program  
and erase commands  
Hardware  
Protected  
(HPM)  
Status Register is Hardware write protected.  
The values in the SRWD, BP2, BP1 and BP0  
bits cannot be changed.  
Ready to accept Page  
Program and Sector Erase  
commands  
Protected against program  
and erase commands  
0
1
Note  
As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 7.1 on page 11.  
Table 9.4 shows that neither W# or SRWD bit by themselves can enable HPM. The device can enter HPM  
either by setting the SRWD bit after driving W# low, or by driving W# low after setting the SRWD bit.  
However, the device disables HPM only when W# is driven high.  
Note that HPM only protects against changes to the status register. Since BP2:BP0 cannot be changed in  
HPM, the size of the protected area of the memory array cannot be changed. Note that HPM provides no  
protection to the memory array area outside that specified by BP2:BP0 (Software Protected Mode, or SPM).  
If W# is permanently tied high, HPM can never be activated, and only the SPM (BP2:BP0 bits of the Status  
Register) can be used.  
9.9  
Page Program (PP)  
The Page Program (PP) command changes specified bytes in the memory array (from 1 to 0 only). A WREN  
command is required prior to writing the PP command.  
The host system must drive CS# low, and then write the PP command, three address bytes, and at least one  
data byte on SI. CS# must be driven low for the entire duration of the PP sequence. The command sequence  
is shown in Figure 9.9 and Table 9.5.  
The device programs only the last 256 data bytes sent to the device. If the number of data bytes exceeds this  
limit, the bytes sent before the last 256 bytes are discarded, and the device begins programming the last 256  
bytes sent at the starting address of the specified page. This may result in data being programmed into  
different addresses within the same page than expected. If fewer than 256 data bytes are sent to device, they  
are correctly programmed at the requested addresses.  
The host system must drive CS# high after the device has latched the 8th bit of the data byte, otherwise the  
device does not execute the PP command. The PP operation begins as soon as CS# is driven high. The  
device internally controls the timing of the operation, which requires a period of tPP. The Status Register may  
be read to check the value of the Write In Progress (WIP) bit while the PP operation is in progress. The WIP  
bit is 1 during the PP operation, and is 0 when the operation is completed. The device internally resets the  
Write Enable Latch to 0 before the operation completes (the exact timing is not specified).  
The device does not execute a Page Program (PP) command that specifies a page that is protected by the  
Block Protect bits (BP2:BP0) (see Table 7.1 on page 11).  
20  
S25FL040A  
S25FL040A_00_B0 August 31, 2006