CXD1968AR
SMOOTH_CTRL
Read/Write
RESET: 0x04
Default R/W
Offset Address: 0xB4
Bit
Name
Description
00: 8MHz channel
01: 7MHz channel
10: 6MHz channel
11: Reserved
7:6 CHANNEL_WIDTH
5:3 Reserved
Channel width
00
R/W
000
1
R/W
R/W
0: Smoothing circuit not in its reset state
1: Smoothing circuit is held in its reset state
2
RESET
0: Data period value can be updated manually (via I2C) or
left at its default setting.
1: Update data period value automatically from received
TPS information.
1
DATA_PERIOD_AUTO
0
0
R/W
R/W
0: Disable smoothing circuit. When disabled, the input to
the smoothing circuit is routed to the output without
going through the smoothing FIFO.
0
ENABLE
1: Enable smoothing circuit.
SMOOTH_STAT
Read/Write
Description
RESET: 0x00
Default R/W
Offset Address: 0xB5
Bit
Name
7:2 Reserved
00h
R/W
1: An underflow condition has been detected.
An underflow condition is where data is requested but cannot
be provided because the read FIFO is empty.
Note that when data is requested but not provided because
the next TS word is a sync-byte and the FIFO does not contain
a complete TS packet, this condition is part of the smoothing
blocks normal operation and is not classed as an underflow
condition.
1
0
UNDERFLOW
0
R/W
Write a “1” to this location to clear this bit.
1: An overflow condition has been detected.
Write a “1” to this location to clear this bit.
OVERFLOW
0
R/W
SMOOTH_DELAY
Read/Write
Description
RESET: 0x14
Offset Address: 0xB6
Bit
Name
Default
14h
Bit
The value in this register represents the data path delay in
transport stream packets between the COFDM core and the
data smoothing block.
7:0 DELAY
R/W
This information is used by the smoothing circuit to determine
the delay between TPS bit changes and the associated
modification to the transport stream output data rate.
- 92 -
SONY [ SONY CORPORATION ]
